Logic World Wiki - User contributions [en]

Talk:Edge Detection

2025-10-08T15:54:57Z

DjSapsan: /* Edge detection circuit diagram output is not delayed */ Reply

== Edge detection circuit diagram output is not delayed ==

@[[User:N00basaurus|N00basaurus]], in the circuit diagram you show (not lw), the output immediately becomes 1 as soon as the input becomes 1, whereas in logicworld the behaviour would be a bit different, in that the output would be delayed by one tick. I'd propose delaying the output by 1 tick in the diagram to not 'bait' people into thinking they could build such a circuit even though they cannot. [[User:GHXX|GHXX]] ([[User talk:GHXX|talk]]) 18:54, 7 October 2025 (UTC)

:@[[User:GHXX|GHXX]] btw i made that diagram. I thought about it, but the article is about rising edge. The LW behavior is shown on the last screenshot.
:Maybe we can leave the screenshot alone for demonstration. And instead of the diagram make a drawing that just highlights the rising edge without considering ticks [[User:DjSapsan|DjSapsan]] ([[User talk:DjSapsan|talk]]) 15:54, 8 October 2025 (UTC)

Control Unit

2025-10-07T18:40:08Z

DjSapsan: improved formatting

; '''Control Unit'''
: In ''Logic World'', a '''Control Unit''' ('''CU''') is a composite component designed to generate and coordinate control signals for other circuits.
: Its primary functions are:
# To produce ordered sequences of control signals over time
# To provide a convenient interface that prevents mistaken combinations of control signals

== Overview ==

All computers, however complex, are built on a fundamental idea: changing from one state to another state.
By sequencing control signals in various combinations, any computation can be achieved.

Each transfer of information inside the computer requires one ''read'' signal and one ''write'' signal.
For example, transferring information from one [[Register]] to another involves first activating the read signal on the source register, then the write signal on the destination register.
The control unit is responsible for generating these signals in the correct order.

More elaborate control sequences, such as performing operations on data or displaying results on a [[Display]], are similarly coordinated by the control unit.

A control unit can adjusts its sequence of control signals based on different input conditions.
These inputs typically originate from other components such as the [[Instruction Register]], [[Status Register]], or various system flags.
By interpreting these inputs, the control unit can "execute an instruction" - dynamically altering its control signal sequence according to the contents of the instruction register.

The control unit may also update the instruction register by fetching new data from memory.
This operation, known as an ''instruction fetch'', is part of the core fetch → decode → execute cycle present in virtually all computer architectures.
The overall timing of these operations is usually governed by a [[Clock]].

== Implementation ==

=== Pipeline Computers ===
In [[Pipeline Computer]] architectures, control signals are often generated using a series of shift registers.
Each register passes its state to the next on the [[Edge Detection|rising edge]] of the clock.
Each stage of the pipeline corresponds to one register and produces its control signals through devices such as [[Decoder]]s, [[Lookup Table]]s, [[Programmable Logic Array|PLAs]], or [[ROM]]s.
As new states are shifted through the pipeline, each stage updates its control signals accordingly.

=== Sequential Computers ===
For non-pipelined (sequential) computers, control logic is generally more complex.
While a simple design can use a [[Counter]] and a [[ROM]] to step through predefined control sequences, systems that require conditional branching or loops typically implement their control unit as a [[Finite State Machine]] (FSM).
This approach allows for flexible control flow and dynamic sequencing based on internal and external conditions.

Clock

2025-10-07T18:21:23Z

DjSapsan: fixed some wording and added diagrams

A '''Clock''' is a [[circuit]] that changes its output state periodically over time.

The simplest clock is made of a single [[Inverter]] connected to itself, either directly or with a delay.
A single inverter clock alternates {{on}} and {{off}} every [[tick]].
With [[Delayer|delayer]] components, it will have a longer period.

== Terminology ==
:'''Period''' is the duration of the entire cycle of the clock, measured in ticks. It includes the duration of the {{on}} output and the {{off}} output.

:'''Duration''' of a signal is the number of ticks the signal remains unchanged.

:'''Frequency''' is the rate at which the clock repeats its cycle. It shows how many full cycles (periods) occur per unit of time.

==== Measuring frequency ====
In ''Logic World'', the simulation runs at a adjustable ''[[Tick|Tick Rate]]'' (number of ticks per second).
Since period is measured in ticks, the real-time frequency can be calculated as:

::<math>f_{Hz} = \frac{\text{Tick Rate}}{\text{Period}}</math>

For example, with a tick rate of 60 and a clock period of 12 ticks:

::<math>f_{Hz} = \frac{60}{12} = 5\ \text{Hz}</math>

Increasing the tick rate or reducing the clock period increases frequency.

==== Measuring delays ====
With delay components, the duration of a signal is calculated as follows:

:<math>duration = delay + 1</math>

The full period will be:

:<math>2 \times (delay + 1)</math>
{| width="100%"
|
[[File:Not-clock.png|thumb|left|alt=Not-clock|A single inverter]]
|
[[File:Delayer-clock.png|thumb|right|alt=Not-Clock|An inverter with a delayer, this example has a period of 22 ticks]]
|}

In advanced circuits or during construction you may require clocks with different periods, signal shapes, and functionality. Good clocks are essential in complex designs.

== Clock signal diagrams ==
Below are examples of different clock signals patterns for better understanding:

{{Binary signal
| signals=Alternating, Square, Pulsating, Complex
| signal1=101010101010101010
| signal2=111100001111000011
| signal3=100010001000100010
| signal4=110000110000110000
}}

== Construction ==
This article is mostly agnostic towards the period of the clock. This means you may add different features that will work regardless of the period.

To make a good clock you need to know what functionality you require. Here is a list of possible features you may want:
#Turning on/off
#Manually adjustable period
#Digitally adjustable period
#Specific signal shape

This article will show how to add features to a clock, starting from the simplest to the most advanced.

=== Turning on/off ===
[[File:Clock-off.png|thumb|right|alt=Clock turned off by a switch|Clock turned off by a switch]]
Any clock has an inverter, therefore it can always be turned off by applying an {{on}} signal to it.
It is good practice to add a switch to every clock.
If you want to use [[Button|buttons]] to turn the clock on/off, you can add a [[T Flip-Flop]], a [[Set-Reset Flip-Flop]], or similar components.

=== Adjustable period ===
[[File:Adjust-delayer.png|thumb|right|alt=Delayer can be adjusted, up to 30 ticks.|Delayer can be adjusted, up to 30 ticks.]]

You can adjust the period either manually or digitally.
If you are using a [[delayer]], you can [[editing|edit]] its delay up to 30 [[tick|ticks]]. Remember that with the inverter, the total duration will be 1 tick longer.
For periods longer than 30 ticks, connect several delayers in series.

Another approach is to build multiple clocks with different periods and enable one of them.
This method also allows digital or programmatic period control by selecting the clock with the required period, usually with a [[multiplexer]].
<div style="clear:right;"></div>

=== Signal shape ===
Simple clock will have a "square wave" signal, where output is alternating between {{on}} and {{off}} with an equal duration. Quite often you will need a clock with a long period but producing a 1 tick pulse each cycle.
It is possible to achieve this by building a loop with multiple buffers and passing a 1-tick signal through it, but it will quickly become impractical.<br>
A more efficient way is to attach a separate [[pulse generator]] to a normal clock. It will work with any clock configuration.<br>
For long periods and long pulses, you can use the following design: clock → pulse generator → signal extender.

== "Multitool" clock example ==
[[File:Mutliclock.png|frameless|right|alt=Multiclock with all the features|Multiclock with all the features]]
It is a good idea to construct a small but efficient clock for general use. The example on the right screenshot combines all key features: a power switch, adjustable period, and pulse output. It's a good idea to have it saved as a [[subassembly]].
The total period here is 8 ticks, and you can see the signal shape on the next screenshot below.

[[File:Oscilloscope.png|none|center|alt=Oscilloscope showing the shape of the signal|Oscilloscope showing the shape of the signal]]

Edge Detection

2025-10-07T18:03:09Z

DjSapsan: /* Circuit Implementation */

'''Edge detection''' is the process of sending a signal at the moment a signal transitions.

A '''rising edge''' refers to the instant when a signal changes from ''off'' to ''on''.

A '''falling edge''' refers to the instant when a signal changes from ''on'' to ''off''.

== Construction ==
[[File:Raising-edge-detector.png|thumb|right|alt=Raising edge detector|Raising edge detector]]
You can detect a rising edge by checking whether the input signal was ''off'' some number of [[Tick|ticks]] ago but is now ''on''.

This can be done using an [[AND Gate]] and an [[Inverter]].
Connect one input of the AND gate directly to your signal, and connect the other input through the inverter.

When the input signal turns on, the direct input to the AND gate is immediately on. The inverter output, however, is delayed by 1 tick, so it remains ''on'' for one more tick.
Since both inputs of the AND gate are ''on'', it becomes marked for activation in the next tick.

On the next tick, the AND gate turns ''on'' while the inverter output turns ''off''. At this point, not all AND gate inputs are ''on'', so it will be marked to turn ''off'' on the following tick.

The pulse length is determined by the delay between the direct and inverted inputs of the AND gate.
You can extend the pulse to 2 ticks using a [[Buffer]], or make it 2 ticks or longer with a [[Delayer]].

== Example Signal Diagram ==
Below is an example timing diagram showing how a rising edge detector behaves:
* '''Input''' shows the original signal toggling between off and on.
* '''Output''' is the short pulse generated on each rising edge of the input signal.

{{Binary signal
| signals=Input, Output
| signal1=000011110000111
| signal2=000010000000100
}}

How it looks in the Logic World:
[[File:edge-oscillator.png|frame|center|alt=oscilloscope|Raising Edge on oscilloscope ]]

Edge Detection

2025-10-07T18:02:13Z

DjSapsan: improved formatting and did todo

'''Edge detection''' is the process of sending a signal at the moment a signal transitions.

A '''rising edge''' refers to the instant when a signal changes from ''off'' to ''on''.

A '''falling edge''' refers to the instant when a signal changes from ''on'' to ''off''.

== Circuit Implementation ==
[[File:Raising-edge-detector.png|thumb|right|alt=Raising edge detector|Raising edge detector]]
You can detect a rising edge by checking whether the input signal was ''off'' some number of [[Tick|ticks]] ago but is now ''on''.

This can be done using an [[AND Gate]] and an [[Inverter]].
Connect one input of the AND gate directly to your signal, and connect the other input through the inverter.

When the input signal turns on, the direct input to the AND gate is immediately on. The inverter output, however, is delayed by 1 tick, so it remains ''on'' for one more tick.
Since both inputs of the AND gate are ''on'', it becomes marked for activation in the next tick.

On the next tick, the AND gate turns ''on'' while the inverter output turns ''off''. At this point, not all AND gate inputs are ''on'', so it will be marked to turn ''off'' on the following tick.

The pulse length is determined by the delay between the direct and inverted inputs of the AND gate.
You can extend the pulse to 2 ticks using a [[Buffer]], or make it 2 ticks or longer with a [[Delayer]].

== Example Signal Diagram ==
Below is an example timing diagram showing how a rising edge detector behaves:
* '''Input''' shows the original signal toggling between off and on.
* '''Output''' is the short pulse generated on each rising edge of the input signal.

{{Binary signal
| signals=Input, Output
| signal1=000011110000111
| signal2=000010000000100
}}

How it looks in the Logic World:
[[File:edge-oscillator.png|frame|center|alt=oscilloscope|Raising Edge on oscilloscope ]]

File:Edge-oscillator.png

2025-10-07T18:00:57Z

DjSapsan:

Edge-oscillator

File:Raising-edge-detector.png

2025-10-07T17:58:24Z

DjSapsan:

Raising edge detector

Finite State Machine

2025-10-07T17:48:31Z

DjSapsan: improved formatting

; '''Finite State Machine'''
: In ''Logic World'', a '''Finite State Machine''' ('''FSM''') is a circuit that produces a sequence of states and output signals depending on input conditions and a defined state graph.

== Construction ==
An FSM is constructed using either a [[ROM]] or a [[Programmable Logic Array]] (PLA), with some or all of the component’s outputs connected back to its inputs through a [[Register]].
The register stores the current state, while the ROM or PLA defines the transition logic that determines the next state.

This structure allows the circuit to map one list of states to another.
For example, if you define transitions <code>1 → 2</code>, <code>2 → 3</code>, <code>3 → 5</code>, <code>5 → 8</code>, and <code>8 → 13</code>, then each register pulse will produce the sequence <code>1, 2, 3, 5, 8, 13</code>.
When you add a transition <code>13 → 1</code>, the graph becomes cyclic and the sequence repeats indefinitely.

== Conditional Transitions ==
FSMs can use extra inputs as flags to control conditional branching.
For example, you could map <code>3 → 5</code> if input <code>fib</code> is {{on}}, and <code>3 → 4</code> if <code>fib</code> is {{off}}.

{{Todo|Add details for how this condition check is actually implemented}}
{{Todo|Describe how multiple condition checks in the same state are handled}}

If an input should be ignored in a ROM-based FSM, you must duplicate the same state mapping twice—once for the input being {{on}} and once for {{off}}—so that the transition occurs regardless of input state.
In contrast, if you use a PLA, you can simply leave the unused input unconnected.

== Output Generation ==
A state machine can also produce output signals in each state.

This can be done by connecting a [[Lookup Table]] to the register’s output and assigning each valid state a corresponding output pattern.
Such a configuration is known as a '''[[wikipedia:Moore_machine|Moore machine]]''', where outputs depend solely on the current state.

Alternatively, outputs can depend on both the current state and the inputs by synchronizing them with another register.
This allows the FSM to select a new output combination during state transitions.
Such a setup is known as a '''[[wikipedia:Mealy_machine|Mealy machine]]'''.

{{Todo|Describe the advantages each machine has}}

Programmable Logic Array

2025-10-07T17:41:49Z

DjSapsan: better formatting

; '''Programmable Logic Array'''
: A '''Programmable Logic Array''' ('''PLA''') is a combinational logic component that allows encoding of any Boolean expression into a simple, repeating circuit, provided that the expression is rearranged into a [[wikipedia:Disjunctive_normal_form|sum-of-products]] form.

{{Todo|Add a basic PLA example and explain its function.}}

== See also ==
* [[Lookup_Table|Lookup table]]

Programmable Logic Array

2025-10-06T15:00:08Z

DjSapsan:

A Programmable Logic Array, or PLA, is a combination logic component that allows you to encode any boolean expression into a simple, repeating circuit, provided the boolean expression is rearranged as a [[wikipedia:Disjunctive_normal_form|sum-of-products]] form.

{{Todo|Add a basic PLA example, explain what it's doing}}

== See also ==
[[Lookup_Table|Lookup table]]

Register

2025-10-04T21:26:19Z

DjSapsan: Created article about registers

{{Register}}

It is one of the most basic memory circuits in ''Logic World'' and serves as a building block for [[Random-access_memory|RAM]], [[CPU]]s, and many other digital systems.
Sometimes registers are called cells.

== Overview ==

A register can store data and output it later on demand.
Each register has the following connections:
# Data input
# Write signal
# Read signal
And the output:
# Data output

[[File:Register-basic.png|thumb|right|alt=Basic 8-bit register|Basic 8-bit register using D Latches]]
Registers are often used to hold intermediate results, counters, addresses, or any temporary data in larger circuits.
In some cases, the data inside the register is treated as multiple values.
<div style="clear:right;"></div>

== Variants ==
Simple registers read or write all bits simultaneously.
However, there are different variations that differ by design or purpose. Common variants include:

* '''Shift register''' — supports shifting bits inside on command. Variations include shifting to the left, right, or both. Shifting can be rotational or non-rotational.
* '''Parallel-in serial-out (PISO)''' — bits are stored all at once, but read serially, bit by bit.
* '''Serial-in parallel-out (SIPO)''' — bits are stored one by one, but read all at once.
* '''Serial-in serial-out (SISO)''' — bits are stored one by one and read serially, bit by bit.

== Construction ==
Registers are built using trigger or latch components. There are many variants, and any of them can be used to construct a register.
The simplest option is the [[D_Latch|D Latch]]. A register that stores multiple bits using D Latches is constructed by placing a row of D Latches and connecting all storage and read circuits together. The example is shown in the first screenshot above.
Serial variations are constructed by connecting D Latches to each other in series instead of in parallel.

=== Write operation ===
When the write input is active, the register copies its data input into its internal storage. The value remains stored even if the write signal is turned {{off}}.

=== Read operation ===
[[File:register-RW.png|thumb|right|alt=8-bit register|An 8-bit register with read/write controls]]
All memory elements have the stored bit always active, so for better control over reading, especially when many registers share the same data bus, you may need to add an additional part to actually send the stored data. This is done by attaching outputs to [[AND_Gate|AND gates]] or [[relay|relays]].
In serial-out variations, only the last one element is the output.
<div style="clear:right;"></div>

== Example usage ==

Registers are essential in circuits that need to remember or reuse values:
* Holding the current instruction in a [[CPU]]
* Holding bit flags
* Sending or receiving data over distance
* Storing a loop counter
* Acting as temporary memory, like a [[cache]] for [[RAM]]

== See also ==
* [[Random-access_memory|RAM]]
* [[Trigger]]
* [[Flip Flop]]
* [[Latch]]

File:Register-RW.png

2025-10-04T21:16:19Z

DjSapsan:

File:Register-basic.png

2025-10-04T20:54:19Z

DjSapsan:

Template:Register

2025-10-04T20:47:08Z

DjSapsan:

; '''Register'''
:In ''Logic World'', a '''register''' is a small [[circuit]] used to store certain number of bits as a single value.
:Unlike [[Random-access_memory|RAM]], it doesn't have multiple independent cells.

Template:Register

2025-10-04T20:29:35Z

DjSapsan: Created template for a register

; '''Register'''
:In ''Logic World'', a '''register''' is a small [[circuit]] used to store one value.
:Unlike [[Random-access_memory|RAM]], it doesn't have multiple independent cells.

Clock

2025-10-04T20:16:54Z

DjSapsan: added more details

A '''Clock''' is a [[circuit]] that changes its output state periodically over time.

The simplest clock is made of a single [[Inverter]] connected to itself, either directly or with a delay.
A single inverter clock alternates {{on}} and {{off}} every [[tick]].
With [[Delayer|delayer]] components, it will have a longer period.

== Terminology ==
:'''Period''' is the duration of the entire cycle of the clock, measured in ticks. It includes the duration of the {{on}} output and the {{off}} output.

:'''Duration''' of a signal is the number of ticks the signal remains unchanged.

:'''Frequency''' is the rate at which the clock repeats its cycle. It shows how many full cycles (periods) occur per unit of time.

==== Measuring frequency ====
In ''Logic World'', the simulation runs at a adjustable ''Tick Rate'' (number of ticks per second).
Since period is measured in ticks, the real-time frequency can be calculated as:

::<math>f_{Hz} = \frac{\text{Tick Rate}}{\text{Period}}</math>

For example, with a tick rate of 60 and a clock period of 12 ticks:

::<math>f_{Hz} = \frac{60}{12} = 5\ \text{Hz}</math>

Increasing the tick rate or reducing the clock period increases frequency.

==== Measuring delays ====
With delay components, the duration of a signal is calculated as follows:

:<math>duration = delay + 1</math>

The full period will be:

:<math>2 \times (delay + 1)</math>
{| width="100%"
|
[[File:Not-clock.png|thumb|left|alt=Not-clock|A single inverter]]
|
[[File:Delayer-clock.png|thumb|right|alt=Not-Clock|An inverter with a delayer, this example has a period of 22 ticks]]
|}

In advanced circuits or during construction you may require clocks with different periods, signal shapes, and functionality. Good clocks are essential in complex designs.

== Construction ==

This article is mostly agnostic towards the period of the clock. This means you may add different features that will work regardless of the period.

To make a good clock you need to know what functionality you require. Here is a list of possible features you may want:
#Turning on/off
#Manually adjustable period
#Digitally adjustable period
#Specific signal shape

This article will show how to add features to a clock, starting from the simplest to the most advanced.

=== Turning on/off ===
[[File:Clock-off.png|thumb|right|alt=Clock is turned off by the switch|Clock is turned off by the switch]]
Any clock has an inverter, therefore it can always be turned off with an {{on}} signal applied to it.
It's good practice to add a switch to all clocks.
You can also use buttons to turn on/off the clock. With 1 button you will need a [[T Flip Flop]]. With 2 buttons you can use a [[Set Reset Trigger]].

=== Adjustable period ===
You can adjust the period either manually or digitally.

[[File:Adjust-delayer.png|thumb|right|alt=Delayer can be adjusted, up to 30 ticks.|Delayer can be adjusted, up to 30 ticks.]]
If you are using a [[delayer]] you can [[editing|edit]] its delay up to 30 [[tick|ticks]]. Remember that with the inverter, the total duration will be 1 tick longer.
For more than 30 ticks, you will need to connect several delayers one after another.

Another approach is to build several clocks with different periods and enable one of them.
With this approach you can also control the period digitally or programmatically, by selecting the clock with the required period, usually by a [[multiplexer]].
<div style="clear:right;"></div>

=== Signal shape ===
Simple clock will have a "square wave" signal, where output is alternating between {{on}} and {{off}} with an equal duration. Quite often you will need a clock with a long period but producing a 1 tick pulse each cycle.
It is possible to achieve this by building a loop with multiple buffers and passing a 1-tick signal through it, but it will quickly become impractical.<br>
A more efficient way is to attach a separate [[pulse generator]] to a normal clock. It will work with any clock configuration.<br>
For long periods and long pulses, you can use the following design: clock → pulse generator → signal extender.

== "Multitool" clock example ==
[[File:Mutliclock.png|frameless|right|alt=Multiclock with all the features|Multiclock with all the features]]
It is a good idea to construct a small but efficient clock for general use. The example on the right screenshot combines all key features: a power switch, adjustable period, and pulse output. It's a good idea to have it saved as a [[subassembly]].
The total period here is 8 ticks, and you can see the signal shape on the next screenshot below.

[[File:Oscilloscope.png|none|center|alt=Oscilloscope showing the shape of the signal|Oscilloscope showing the shape of the signal]]

Clock

2025-10-02T22:32:20Z

DjSapsan: Completed the article

A '''Clock''' is a [[circuit]] that changes its output state periodically over time.

The simplest clock is made of a single [[Inverter]] connected to itself, either directly or with a delay.
A single inverter clock alternates {{on}} and {{off}} every [[tick]].
With [[Delayer|delayer]] components, it will have a longer period.

== Terminology ==
:'''Period''' is the duration of the entire cycle of the clock, measured in ticks. It includes the duration of the {{on}} output and the {{off}} output.

:'''Duration''' of a signal is the number of ticks the signal remains unchanged.

With delay components the duration of a signal is calculated as follows:

:<math>duration = delay + 1</math>

The full period will be:

:<math>2 \times (delay + 1)</math>

{| width="100%"
|
[[File:Not-clock.png|thumb|left|alt=Not-clock|A single inverter]]
|
[[File:Delayer-clock.png|thumb|right|alt=Not-Clock|An inverter with a delayer, this example has a period of 22 ticks]]
|}
In advanced circuits or during construction you may require clocks with different periods, signal shapes, and functionality. Good clocks are essential in complex designs.

== Construction ==

This article is mostly agnostic towards the period of the clock. This means you may add different features that will work regardless of the period.

To make a good clock you need to know what functionality you require. Here is a list of possible features you may want:
#Turning on/off
#Manually adjustable period
#Digitally adjustable period
#Specific signal shape

This article will show how to add features to a clock, starting from the simplest to the most advanced.

=== Turning on/off ===
[[File:Clock-off.png|thumb|right|alt=Clock is turned off by the switch|Clock is turned off by the switch]]
Any clock has an inverter, therefore it can always be turned off with an {{on}} signal applied to it.
It's good practice to add a switch to all clocks.
You can also use buttons to turn on/off the clock. With 1 button you will need a [[T Flip Flop]]. With 2 buttons you can use a [[Set Reset Trigger]].

=== Adjustable period ===
You can adjust the period either manually or digitally.

[[File:Adjust-delayer.png|thumb|right|alt=Delayer can be adjusted, up to 30 ticks.|Delayer can be adjusted, up to 30 ticks.]]
If you are using a [[delayer]] you can [[editing|edit]] its delay up to 30 [[tick|ticks]]. Remember that with the inverter, the total duration will be 1 tick longer.
For more than 30 ticks, you will need to connect several delayers one after another.

Another approach is to build several clocks with different periods and enable one of them.
With this approach you can also control the period digitally or programmatically, by selecting the clock with the required period, usually with a [[multiplexer]].
<div style="clear:right;"></div>

=== Signal shape ===

Quite often you will need a clock with a long period, but produces 1 tick pulse each cycle.
It is possible to achieve this by building a loop with multiple buffers and passing a 1-tick signal through it, but it will quickly become impractical.<br>
A more efficient way is to attach a separate [[pulse generator]] to a normal clock. It will work with any clock configuration.<br>
For long periods and long pulses, you can use the following design: clock → pulse generator → signal extender.

== "Multitool" clock example ==
[[File:Mutliclock.png|frameless|right|alt=Multiclock with all the features|Multiclock with all the features]]
The total period here is 8 ticks, and you can see the signal shape on the next screenshot.
It is a good idea to construct a small but efficient clock for general use.
It should have everything described above. The screenshot below demonstrates an example. It has a turn-off switch, adjustable period, and a pulse output.

[[File:Oscilloscope.png|none|center|alt=Oscilloscope showing the shape of the signal|Oscilloscope showing the shape of the signal]]

File:Oscilloscope.png

2025-10-02T22:23:23Z

DjSapsan:

Oscilloscope showing a shape of the signal

File:Mutliclock.png

2025-10-02T22:21:24Z

DjSapsan:

Mutliclock with all the features

Talk:Multiplexer

2025-10-02T22:04:05Z

DjSapsan: /* A better example or diagram */ new section

== A better example or diagram ==

In the article the first diagram is not matching the circuit below. It will be confusing for inexperienced readers. Maybe they need to match or maybe it can demonstrate both cases - 1 bit and 4 bits [[User:DjSapsan|DjSapsan]] ([[User talk:DjSapsan|talk]]) 22:04, 2 October 2025 (UTC)

Editing

2025-10-02T21:57:49Z

DjSapsan: added the hotkey

{{stub}}

'''Editing''' is a [[building mechanic]] that lets you open a menu to change the properties of a [[component]].
It can be done by looking at the component and pressing {{keys|x}}, by default.

Delayer

2025-10-02T21:54:58Z

DjSapsan: Tweaks to the article

{{Infobox component
| title = Delayer
| id = MHG.Delayer
| caption = Delayer set to 10 ticks of delay
| configurable = 1
| io.minInputs = 1
| io.maxInputs = 1
| io.outputs = 1
}}

The '''Delayer''' is a [[component]] used in [[digital logic]]. It propagates signals from its input to its output, similar to a [[Buffer]], but the signal takes more time to propagate, meaning it is delayed.

Delayers are useful for building [[Clock|clock]] circuits.

== Behavior ==

The output of a Delayer reflects the state of the input with a delay.<br>
It will not change state if the new input state is shorter than the configured delay.<br>
The output duration is always at least as long as the delay setting.

{{Truth table
| inputs=Input
| outputs=Output (after delay)
| caption=Delayer truth table
| 0 0
| 1 1
}}

If a Delayer is outputting {{on}}, the input can be briefly turned {{off}} and the output will still remain {{on}}, unless the input is off for longer than the configured delay. This behavior can be useful for maintaining a state in certain circumstances.

== Configurability ==

The length of the delay can be configured by [[editing]] the component.
* Default: 10 ticks
* Minimum: 2 ticks
* Maximum: 30 ticks

== Placement ==

The Delayer can be placed in the center of a [[Circuit Board]] square or on top of a [[Mount]], and can be fine-rotated.

== Tips ==

* To delay for longer than 30 ticks, chain multiple Delayers together.
* To delay for only 1 tick, use a [[Buffer]] instead.

{{Navbox components}}

[[Category:Vanilla components]]
[[Category:Circuitry components]]

File:Adjust-delayer.png

2025-10-02T21:35:03Z

DjSapsan:

Delayer can be adjusted

File:Clock-off.png

2025-10-02T21:24:58Z

DjSapsan:

Clock is turned off by the switch

Clock

2025-09-27T15:41:36Z

DjSapsan: Started working on the clock article

File:Delayer-clock.png

2025-09-27T15:16:18Z

DjSapsan:

Delayer-clock

Random-access memory

2025-09-27T14:57:32Z

DjSapsan: removed stub

{{RAM}}

'''RAM''' is composed of multiple cells that store data, accessed by an address.<br>
It has 4 inputs:
# Data input
# Address input
# Write signal
# Read signal
And 1 output:
# Data output

Each cell in RAM is essentially a [[register]].

Building a RAM from scratch is one of the best ways to start learning logic and computers, as well as to get familiar with circuit construction in ''Logic World''.

RAMs can have very different designs, specifications, and can be [[Optimization|optimized]] for speed, size, or even aesthetics. RAM designs are usually specified by the following parameters:
# Address size
# Data size
# Delay during retrieving/storing data
# Speed between sequential operations

'''Address and data size''' is determined by the number of bits. The total number of combinations using '''n''' bits is <math>2^n</math>.

'''Delay''' during retrieving/storing data is the time between when the read/write signal is turned {{on}} and when the data is retrieved or stored for a single operation.

'''Speed between sequential operations''' is how fast the RAM can run multiple sequential operations. The delay between multiple operations is always <math>\ge</math> the delay for a single operation.

This article will demonstrate a simple RAM with 4 bits for address and 8 bits for data.

== Construction ==

Before constructing a RAM circuit, you need to decide how many memory cells are required and how wide each cell should be.
In the following example, there are 16 memory cells, each 8 bits wide.

Using the formula <math>b = \log_2(x)</math>, you can see that to address 16 different memory cells, 4 bits are needed.
It is possible to use a single [[decoder]] to select the address, but in this example two decoders are used to specify the row and the column of the memory matrix. This makes the structure easier to understand, and also results in decoders that are half the size.

[[File:2-decoders-ram.png|thumb|right|alt=Two 2-bit decoders placed orthogonal|Two 2-bit decoders placed orthogonal]]
On the screenshot, you can see the two decoders placed orthogonally. Above them is the 4-bit address input.
<div style="clear:right;"></div>

[[File:Ram-register.png|thumb|right|alt=A register for a cell|A register for a cell]]
For each cell, we use a simple 8-bit [[register]], shown in the next screenshot.
It has one [[AND_Gate|AND]] gate to combine the row and column signals. This enables the register if it is at the selected intersection.
It also has a separate signal for writing data and another for reading.
<div style="clear:right;"></div>

[[File:Ram-stage-2.png|thumb|right|alt=16 cells placed in a grid|16 cells placed in a grid]]
This register is copied 16 times and arranged into a 4×4 grid. The result is shown on the next screenshot.
<div style="clear:right;"></div>

[[File:Ram-stage-3.png|thumb|right|alt=Address and signal wires connected|Address and signal wires connected]]
The next step is connecting wires from the decoders to the cells, row by row and column by column.
Wires are routed in 3D on top of the cells.
Write and Read signals are also added. The new wiring is highlighted in yellow. The top-left cell (address 0) is selected, but it will not perform any operation unless a Write or Read signal is activated.
<div style="clear:right;"></div>

The last step is connecting the data inputs and outputs.
The input is placed on the top, and all bits are connected to the corresponding inputs of every cell.
The same is done for the output, which is placed on the bottom.

Note that the input and output bits are shared. This is not a problem as long as reading and writing are not performed at the same time.

The final screenshot shows the completed RAM circuit. It has 2 cells with stored data, and it is currently reading from the cell at address 6.

[[File:Ram-final.png|frame|center|alt=Completed RAM circuit, reading data|Completed RAM circuit, reading data]]

== See also ==
* [[Mods:CheeseUtilMod|CheeseUtilMod]] - a mod with RAM components

File:Not-clock.png

2025-09-27T14:55:42Z

DjSapsan:

Not-clock

CPU

2025-09-14T15:43:21Z

DjSapsan: CPU stub

Random-access memory

2025-09-14T15:41:07Z

DjSapsan: RAM construction

{{stub}}
{{RAM}}

'''RAM''' is composed of multiple cells that store data, accessed by an address.<br>
It has 4 inputs:
# Data input
# Address input
# Write signal
# Read signal
And 1 output:
# Data output

Each cell in RAM is essentially a [[register]].

Building a RAM from scratch is one of the best ways to start learning logic and computers, as well as to get familiar with circuit construction in ''Logic World''.

RAMs can have very different designs, specifications, and can be [[Optimization|optimized]] for speed, size, or even aesthetics. RAM designs are usually specified by the following parameters:
# Address size
# Data size
# Delay during retrieving/storing data
# Speed between sequential operations

'''Address and data size''' is determined by the number of bits. The total number of combinations using '''n''' bits is <math>2^n</math>.

'''Delay''' during retrieving/storing data is the time between when the read/write signal is turned {{on}} and when the data is retrieved or stored for a single operation.

'''Speed between sequential operations''' is how fast the RAM can run multiple sequential operations. The delay between multiple operations is always <math>\ge</math> the delay for a single operation.

This article will demonstrate a simple RAM with 4 bits for address and 8 bits for data.

== Construction ==

Before constructing a RAM circuit, you need to decide how many memory cells are required and how wide each cell should be.
In the following example, there are 16 memory cells, each 8 bits wide.

Using the formula <math>b = \log_2(x)</math>, you can see that to address 16 different memory cells, 4 bits are needed.
It is possible to use a single [[decoder]] to select the address, but in this example two decoders are used to specify the row and the column of the memory matrix. This makes the structure easier to understand, and also results in decoders that are half the size.

[[File:2-decoders-ram.png|thumb|right|alt=Two 2-bit decoders placed orthogonal|Two 2-bit decoders placed orthogonal]]
On the screenshot, you can see the two decoders placed orthogonally. Above them is the 4-bit address input.
<div style="clear:right;"></div>

[[File:Ram-register.png|thumb|right|alt=A register for a cell|A register for a cell]]
For each cell, we use a simple 8-bit [[register]], shown in the next screenshot.
It has one [[AND_Gate|AND]] gate to combine the row and column signals. This enables the register if it is at the selected intersection.
It also has a separate signal for writing data and another for reading.
<div style="clear:right;"></div>

[[File:Ram-stage-2.png|thumb|right|alt=16 cells placed in a grid|16 cells placed in a grid]]
This register is copied 16 times and arranged into a 4×4 grid. The result is shown on the next screenshot.
<div style="clear:right;"></div>

[[File:Ram-stage-3.png|thumb|right|alt=Address and signal wires connected|Address and signal wires connected]]
The next step is connecting wires from the decoders to the cells, row by row and column by column.
Wires are routed in 3D on top of the cells.
Write and Read signals are also added. The new wiring is highlighted in yellow. The top-left cell (address 0) is selected, but it will not perform any operation unless a Write or Read signal is activated.
<div style="clear:right;"></div>

The last step is connecting the data inputs and outputs.
The input is placed on the top, and all bits are connected to the corresponding inputs of every cell.
The same is done for the output, which is placed on the bottom.

Note that the input and output bits are shared. This is not a problem as long as reading and writing are not performed at the same time.

The final screenshot shows the completed RAM circuit. It has 2 cells with stored data, and it is currently reading from the cell at address 6.

[[File:Ram-final.png|frame|center|alt=Completed RAM circuit, reading data|Completed RAM circuit, reading data]]

== See also ==
* [[Mods:CheeseUtilMod|CheeseUtilMod]] - a mod with RAM components

File:Ram-final.png

2025-09-14T15:29:54Z

DjSapsan:

Ram-final

Random-access memory

2025-09-14T15:15:28Z

DjSapsan: /* Construction */

{{stub}}
{{RAM}}

'''RAM''' is composed of multiple cells that store data, accessed by an address.<br>
It has 4 inputs:
# Data input
# Address input
# Write signal
# Read signal
And 1 output:
# Data output

Each cell in RAM is essentially a [[register]].

Building a RAM from scratch is one of the best ways to start learning logic and computers, as well as to get familiar with circuit construction in ''Logic World''.

RAMs can have very different designs, specifications, and can be [[Optimization|optimized]] for speed, size, or even aesthetics. RAM designs are usually specified by the following parameters:
# Address size
# Data size
# Delay during retrieving/storing data
# Speed between sequential operations

'''Address and data size''' is determined by the number of bits. The total number of combinations using '''n''' bits is <math>2^n</math>.

'''Delay''' during retrieving/storing data is the time between when the read/write signal is turned {{on}} and when the data is retrieved or stored for a single operation.

'''Speed between sequential operations''' is how fast the RAM can run multiple sequential operations. The delay between multiple operations is always <math>\ge</math> the delay for a single operation.

This article will demonstrate a simple RAM with 4 bits for address and 8 bits for data.

== Construction ==

Before constructing a RAM circuit, you need to decide how many memory cells are required and how wide each cell should be.
In the following example, there are 16 memory cells, each 8 bits wide.

Using the formula <math>b = \log_2(x)</math>, you can see that to address 16 different memory cells, 4 bits are needed.
It is possible to use a single [[decoder]] to select the address, but in this example two decoders are used to specify the row and the column of the memory matrix. This makes the structure easier to understand, and also results in decoders that are half the size.

On the screenshot, you can see the two decoders placed orthogonally. Above them is the 4-bit address input.
[[File:2-decoders-ram.png|thumb|right|alt=Two 2-bit decoders placed orthogonal|Two 2-bit decoders placed orthogonal]]

For each cell, we use a simple 8-bit [[register]], shown in the next screenshot.
It has one [[AND]] gate to combine the row and column signals. This enables the register if it is at the selected intersection.
It also has a separate signal for writing data and another for reading.
[[File:Ram-register.png|thumb|right|alt=A register for a cell|A register for a cell]]

This register is copied 16 times and arranged into a 4×4 grid. The result is shown on the next screenshot.
[[File:Ram-stage-2.png|thumb|right|alt=16 cells placed in a grid|16 cells placed in a grid]]

The next step is connecting wires from the decoders to the cells, row by row and column by column.
Wires are routed in 3D on top of the cells.
Write and Read signals are also added. The new wiring is highlighted in yellow. The top-left cell (address 0) is selected, but it will not perform any operation unless a Write or Read signal is activated.
[[File:Ram-stage-3.png|thumb|right|alt=Address and signal wires connected|Address and signal wires connected]]

The last step is connecting the data input and output.
The input will be placed on the top, and all input bits must be connected to the corresponding inputs of every cell.
The same is done for the output, except it will be placed on the bottom.

== See also ==
* [[Mods:CheeseUtilMod|CheeseUtilMod]] - a mod with RAM components

File:Ram-stage-3.png

2025-09-14T15:12:35Z

DjSapsan:

Ram-stage-3

File:Ram-stage-2.png

2025-09-14T14:52:03Z

DjSapsan:

Ram-stage-2

File:Ram-register.png

2025-09-14T14:48:08Z

DjSapsan:

Ram-register

File:2-decoders-ram.png

2025-09-14T14:41:55Z

DjSapsan:

2-decoders-ram

Arithmetic logic unit

2025-09-14T14:23:01Z

DjSapsan: Tweaks to the article

[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]
[[File:Alu-8-bit.png|thumb|An 8-bit ALU with inputs A, B, !A, !B, Carry, XOR, AND, OR.]]

{{ALU}}
:It may be called the "brains" of the [[CPU|central processor]].
An ALU also has "flags" to keep track of different situations during computation.
Operations that an ALU can perform include arithmetic operations such as addition and subtraction, as well as ''bitwise'' operations like XOR, NOR, AND, and OR.

The status flags it keeps track of are, for example:
* ''A = B''
* ''A > B''
* ''A < B''
* Carry
* Others

ALUs can have very different designs with varying specifications, such as bit size, possible operations, and speed. In principle, you don't need to implement every possible operation - a few operations are sufficient to make the system Turing complete - although additional operations make it more convenient and often faster.

== Example ==
Below is an example of possible operations in an ALU:

{| class="wikitable"
! Name
! Opcode
! Description
|-
| Add
| 000
| Adds A and B
|-
| Sub
| 001
| Subtracts B from A
|-
| AND
| 010
| Outputs true if both A and B are true, otherwise false
|-
| NAND
| 011
| Inverse of AND. If A and B are true, output is false
|-
| OR
| 100
| Outputs true if either A or B is true
|-
| NOR
| 101
| Inverse of OR. If either A or B is true, output is false
|-
| XOR
| 110
| Outputs true if exactly one of A or B is true
|}

Template:ALU

2025-09-14T14:12:31Z

DjSapsan: ALU template

; '''Arithmetic logic unit'''
: In ''Logic World'', an '''arithmetic logic unit''' ('''ALU''') is a component of a [[CPU|central processor]] that performs basic arithmetic and logic operations.
: By combining multiple operations, it is possible to perform any computation.

Building mechanic

2025-09-13T14:11:28Z

DjSapsan: added wiring

{{stub}}

'''Building mechanics''' are tools the player can use to build, i.e. to manipulate [[component]]s and [[wire]]s.

== List of building mechanics ==

* [[Editing]]
* [[Resizing]]
* [[Wiring]]

{{todo|complete this list}}

Random-access memory

2025-09-12T23:25:21Z

DjSapsan: changes

Random-access memory

2025-09-12T23:14:17Z

DjSapsan: RAM stub

{{stub}}
{{RAM}}

RAM is composed of multiple cells that store data and accessed by address.<br>
It has 4 inputs:
#Data input
#Address input
#Write signal
#Read signal
And 1 output:
#Data output

Building a RAM from scratch is the best way to start learning logic and computers, as well as get familiar with building circuits in ''Logic World''.

RAMs can have drastically different designs, have different specifications and [[Optimization|optimized]] for speed/size or even beauty. RAM designs are specified by the following parameters:
#Address size
#Data size
#Delay during retrieving/storing data
#Speed between sequential operations

'''Address and data''' size is determined by number of bits. The total number of combinations, or, in other words, the largest number it can handle with '''n''' bits is <math>2^n</math> .

'''Delay''' during retrieving/storing data is a delay between the read/write signal is turned {{on}} and when the data is retrieved/stored for a singular operation.

'''Speed''' between sequential operations is how fast it can run multiple sequential operations. The speed is <math>\ge</math> delay.

This article will show a simplest RAM with 4 bits for address and 8 bits for data.

== Construction ==

== See also ==
* [[Mods:CheeseUtilMod|CheeseUtilMod]] - a mod with RAM components

Decoder

2025-09-12T22:55:30Z

DjSapsan: /* Construction */

; '''Decoder'''
: In ''Logic World'', a '''Decoder''' is a circuit that takes a binary input and activates one specific output bit corresponding to that input.
: It is commonly used to select one element out of many, for example a cell in memory.
: The Decoder always outputs a single bit.
: Effectively it's translating a binary value into a [[wikipedia:Unary_numeral_system|unary]] value.
: [[File:4bit-decoder.png|alt=4-bit decoder. Input on the left is 1110. The 14th output bit on the right is activated.|thumb|4-bit decoder. Input on the left is 1110. The 14th output bit on the right is activated.]]

== Construction ==

A Decoder is one of the simplest circuits to build.
First, determine how many bits you need.
The number of output bits from input bits is given by:

:<math>o = 2^i</math>

And vice versa:

:<math>i = \log_2(o)</math>

So, if you want 256 outputs, you will need a decoder with 8 input bits.
Each output has a specific pattern of {{on}} and {{off}} bits coming from the input. The circuit is basically a number of [[AND Gate|AND]] gates for each possible combination.

Here are the steps to build it:

* Place a row of input items.
* Connect each input bit to both a [[Inverter|NOT]] gate and a [[Buffer]].The NOT gate is required to have the inverted value and the Buffer is required to match the delay with the NOT gate.
* Place a row of NOT gates to serve as the outputs.
* Go through each output NOT gate and connect them to the corresponding inputs (normal or inverted) to match its binary value. For example, the output corresponding to number 12 (binary 1100) should receive the following binary values:
** 1st bit – normal
** 2nd bit – normal
** 3rd bit – inverted
** 4th bit – inverted
:and so on for each value.

You can design a decoder in different ways. If you are building one for the first time, you may want to explicitly place each wire and gate to match the real electronic analog or to be visually understandable.

When you become more experienced, you can skip unnecessary details and make it as simple as the screenshot above demonstrates. This design, optimized for speed and size, uses the trick of connecting wires from '''output''' pins directly to the required items, avoiding additional buffers and wire routing. On the screenshot below you can see the side view and how it allows it to make it compact.

[[File:Decoder-side.png|thumb|center|alt=Side view of the decoder|Side view of the decoder]]

== Speed ==

The compact design above computes the output in 2 ticks.

== Part of ==

Decoders are used primarily as part of the following circuits:

[[RAM]], [[ROM]]<br>
[[CU|Control Unit]]<br>
[[Multiplexer]], [[Demultiplexer]]<br>
[[Lookup_Table]]<br>

== See also ==
* [[Encoder]]
* [[Lookup Table]]

Decoder

2025-09-12T22:49:21Z

DjSapsan: /* Construction */

; '''Decoder'''
: In ''Logic World'', a '''Decoder''' is a circuit that takes a binary input and activates one specific output bit corresponding to that input.
: It is commonly used to select one element out of many, for example a cell in memory.
: The Decoder always outputs a single bit.
: Effectively it's translating a binary value into a [[wikipedia:Unary_numeral_system|unary]] value.
: [[File:4bit-decoder.png|alt=4-bit decoder. Input on the left is 1110. The 14th output bit on the right is activated.|thumb|4-bit decoder. Input on the left is 1110. The 14th output bit on the right is activated.]]

== Construction ==

A Decoder is one of the simplest circuits to build.
First, determine how many bits you need.
The number of output bits from input bits is given by:

:<math>o = 2^i</math>

And vice versa:

:<math>i = \log_2(o)</math>

So, if you want 256 outputs, you will need a decoder with 8 input bits.
Each output has a specific pattern of {{on}} and {{off}} bits coming from the input. Here are the steps to build it:

* Place a row of input items.
* Connect each input bit to both a [[Inverter|NOT]] gate and a [[Buffer]].The NOT gate is required to have the inverted value and the Buffer is required to match the delay with the NOT gate.
* Place a row of NOT gates to serve as the outputs.
* Go through each output NOT gate and connect them to the corresponding inputs (normal or inverted) to match its binary value. For example, the output corresponding to number 12 (binary 1100) should receive the following binary values:
** 1st bit – normal
** 2nd bit – normal
** 3rd bit – inverted
** 4th bit – inverted
:and so on for each value.

You can design a decoder in different ways. If you are building one for the first time, you may want to explicitly place each wire and gate to match the real electronic analog or to be visually understandable.

When you become more experienced, you can skip unnecessary details and make it as simple as the screenshot above demonstrates. This design, optimized for speed and size, uses the trick of connecting wires from '''output''' pins directly to the required items, avoiding additional buffers and wire routing. On the screenshot below you can see the side view and how it allows it to make it compact.

[[File:Decoder-side.png|thumb|center|alt=Side view of the decoder|Side view of the decoder]]

== Speed ==

The compact design above computes the output in 2 ticks.

== Part of ==

Decoders are used primarily as part of the following circuits:

[[RAM]], [[ROM]]<br>
[[CU|Control Unit]]<br>
[[Multiplexer]], [[Demultiplexer]]<br>
[[Lookup_Table]]<br>

== See also ==
* [[Encoder]]
* [[Lookup Table]]

Template:RAM

2025-09-12T22:36:41Z

DjSapsan: RAM definition

; '''Random-access memory'''
: In ''Logic World'', '''Random-access memory''' ('''RAM''') is a circuit that can store and load data on demand.
: Unlike [[ROM]], the contents of RAM can be changed at any time by writing new data to it.
: Unlike non-random-access memory, access can be performed in ''any'' order with a constant delay for each cell.

Wiring

2025-09-12T22:28:13Z

DjSapsan: added trivia

'''Wiring''' is a [[building mechanic]] that lets you connect wires between different [[component|components]].
Two components can be connected by clicking on the first input/output and then on the second one.

A very useful feature for wiring is Multi-Wire placing.
It allows you to select an entire row of components and connect them to another row of components all at once.

The default way to place the Multi-Wire is the following:
# While holding {{keys|control}}, select the first item and drag the selection to the last item.
# Release all keys. The selected items will become inputs and be highlighted in blue.
# Drag the mouse on the second row to make it the output.

Multi-Wire connection works in all combinations of items: one-to-one, one-to-many, many-to-one, and unequal.
You can also use offsets to select only specific items in the row, for example to skip every second item. The default keys to increase/decrease the offset are {{keys|e}}/{{keys|q}} or mouse wheel up/down. Offset can be done after selecting the inputs or during the selection of outputs.

[[File:Mutli-wire.png|frame|center|alt=Multi-wiring in progress|Multi-wiring in progress]]

== Trivia ==
* Wires have collisions. Using bugs or mods to place wires without collisions is not only a violation of the laws of physics, but is also considered a crime against humanity and must be stopped. You should always see and understand what each wire is doing.
* The maximum length of a wire is 134.

== See also ==
* [[Mods:CustomWirePlacer|CustomWirePlacer]]

Wiring

2025-09-12T22:15:12Z

DjSapsan: Multi-Wire article

'''Wiring''' is a [[building mechanic]] that lets you connect wires between different [[component|components]].
Two components can be connected by clicking on the first input/output and then on the second one.

A very useful feature for wiring is Multi-Wire placing.
It allows you to select an entire row of components and connect them to another row of components all at once.

The default way to place the Multi-Wire is the following:
# While holding {{keys|control}}, select the first item and drag the selection to the last item.
# Release all keys. The selected items will become inputs and be highlighted in blue.
# Drag the mouse on the second row to make it the output.

Multi-Wire connection works in all combinations of items: one-to-one, one-to-many, many-to-one, and unequal.
You can also use offsets to select only specific items in the row, for example to skip every second item. The default keys to increase/decrease the offset are {{keys|e}}/{{keys|q}} or mouse wheel up/down. Offset can be done after selecting the inputs or during the selection of outputs.

[[File:Mutli-wire.png|frame|center|alt=Multi-wiring in progress|Multi-wiring in progress]]

== See also ==
[[Mods:CustomWirePlacer|CustomWirePlacer]]

File:Mutli-wire.png

2025-09-12T22:08:53Z

DjSapsan:

Mutli-wire

Talk:Your First Computer

2025-09-11T14:46:14Z

DjSapsan: /* Discussing the article */ new section

== Discussing the article ==

Hi.
The article must clearly explain that CPU designs can be very different.
It's better to start with showing different possibilities and then building one of the easiest variant.
Here and now I'm talking about the current explanation with ROM and the specific IS. It's not clear that this is only one option and it's not even the most flexible due to ROM. [[User:DjSapsan|DjSapsan]] ([[User talk:DjSapsan|talk]]) 14:46, 11 September 2025 (UTC)

User:DjSapsan/sandbox

2025-09-10T18:18:34Z

DjSapsan: A table for standard

Connectors are described from the 'female' perspective (looking from outside towards it). 'Male' connectors must be complementary.
Groups are ordered from left to right. If they have many layers, then from top to bottom.
Sockets within the group must be stacked together.
Groups of connection items should be divided by a gap between groups. Note if you did otherwise.
Big sockets can be placed in any way.

{| class="wikitable"
| Connector name [.int version] || colspan="8" | name
|-
| Expected speed || colspan="8" | speed
|-
| Expected latency || colspan="8" | latency
|-
! Layer !! Order !! Group name !! Used Bits !! Reserve for other versions !! Socket type !! Direction !! Pulse length in ticks !! Notes
|-
| rowspan="7" | 1 || 1 || Address || 8 || 16 || small || in || ||
|-
| 2 || Data || 8 || 16 || small || both || ||
|-
| 3 || || || || || || ||
|-
| 4 || || || || || || ||
|-
| 5 || || || || || || ||
|-
| 6 || || || || || || ||
|-
| 7 || || || || || || ||
|-
| rowspan="4" | 2 || 1 || || || || || ||
|-
| 2 || || || || || || ||
|-
| 3 || || || || || || ||
|-
| 4 || || || || || || ||
|-
| colspan="9"|short description and how to work ||
|-
| colspan="9"| img ||
|}

Standardization

2025-09-10T18:03:05Z

DjSapsan: created stub for the new article about Standardization

{{stub}}

; '''Standardization'''
: In ''Logic World'', '''Standardization''' is the process of creating and agreeing on a set of consistent technical specifications, protocols and practices to ensure compatibility between different devices made by different people.