Logic World Wiki - User contributions [en]

Your First Computer

2025-10-18T00:27:37Z

N00basaurus: Expanded the Building a Computer portion of the guide.

{{stub}}

== Introduction ==
This guide is for anyone who is interested in learning how computers work, and wants to learn by building a computer for themselves, but doesn't know where to start.

This guide assumes the reader has a basic understanding of Logic Worlds [[Building mechanic|building mechanics]], and has some experience building some of the more intermediate components, such as [[Full Adder|adders]], [[Random-access memory|memory]], and [[decoder|decoders]]. As well as at least some understanding of the [[wikipedia:Binary_number|binary numbers system]].

The first part of this guide will go over the hardware of a very basic computer system. This guide will not be covering things like text and image processing, internet browsing, operating systems, file systems, windows and graphical user interfaces and other systems generally associated with personal computers. These systems are all built using software, and covering them, as well as software in general, is an entire subject unto itself. This guide will only be focusing on creating hardware that can execute software. Furthermore, this guide will only be focusing on ''core'' hardware, the bare minimum required to run software. This guide will not be covering peripheral hardware such as screens, graphics processor units, storage devices, co-processors, or multi-core setups. Nor will this guide be covering the topic of source code compilation. These are all topics that require their own study and as such are outside the scope of this guide.

The second part of this guide will be covering the process of designing your computer. It will bring up key details you should consider when planning your computer build, as well as providing a basic layout that you can use if you don't want to design everything from scratch yourself.

The third part will of this guide will cover building your computer.

== Hardware Theory ==
All computers, regardless of complexity, need at least these 4 components. Program memory typically made using [[ROM|read-only memory]], an [[Arithmetic logic unit|ALU]], working memory typically made using individual [[Register|registers]] and [[random-access memory]], and a [[Control Unit|control unit]].
[[File:Computer_Structure_diagram.png|right|thumb|300x300px|The structure of the computer in this article]]
Program memory is where the program to be executed is stored. It takes the form of a list of binary numbers called machine code, and each number is called an instruction or opcode. The computer will step through this list one instruction at a time, grabbing each instruction, interpreting it, and performing an action corresponding to that instruction. This process is referred to as the fetch-decode-execute cycle.

Actions that a computer can perform can vary greatly, but two of the most common actions are moving data around, and performing operations using data.

The ALU is what allows a computer to perform these operations, and working memory is where the data being operated on is stored.

Moving data around may seem pointless at first, but often ALU's don't have direct access to working memory, but instead must use whatever is stored in more local registers. Data must therefore be juggled between working memory and registers in order to give the ALU access to the entire dataset. It's also useful for organizing data into larger data structures.

While it might be hard to wrap your head around this at first, everything that computers do can mostly be reduced to these two operations: moving data around, and operating on data. How these two operations can be structured to do things like browse the internet or play games requires a study of software, and is thus outside the scope of this article. But under the hood, millions of these operations are happening at a rate of billions a second, and it's this size and speed that allows computers to perform much more complicated tasks.
[[File:A schematic view of a very basic control unit.png|thumb|A lookup table takes in as its inputs the content of a step counter and an instruction register, and produces as its outputs various read, write, and function signals. On the clocks rising edge, the step counter is incremented. The lookup table immediately updates its outputs, reading from various components and sending function signals. The write signals do not get sent out though until the falling edge of the clock. As this diagram suggests, the lookup table is in control of its own instruction register, and has the ability to reset the step counter. The instruction register is updated at the beginning of every instruction sequence, and the step counter is reset at the end of every instruction sequence.]]
Coordinating these instruction fetches, data moves, and ALU operations is the control unit. It's job is to decode the instruction fetched from program memory and decide what control signals to send out and when.

While this module can get very complicated, the simplest control unit consists of a [[Lookup Table|lookup table]] that takes the current instruction and the value of a [[counter]] as a combined input, and produces all the read, write, and function signals the computer needs as an output. A clock is used to increment the counter, and to a pulse for the write signals through the use of a [[Edge Detection|falling edge detector]], while the table is configured to read from program memory and write to an instruction register when the counter is 0, then increment an instruction pointer register when the counter is 1. From there, the table can be configured to do different things depending on the value of the instruction register. The counter register is reset when the instruction is complete, and the fetch-decode-execute cycle repeats.

On top of being able to move data around and perform operations, there is a third common type of action a computer can perform called a control flow instruction. These consist of instructions like jumping, conditional branching, calling and returning, and software interrupts. Though we'll only be focusing on jumping and conditional branching here. These all have one thing in common, and that is to break the linear sequence of the program.

Normally, as part of the fetch-decode-execute cycle, the instruction pointer used to index the program memory is incremented after each instruction fetch. Setting up the next instruction in the list to be executed when the current instruction is complete. By writing a new value to the instruction pointer, we queue up a different section of the program memory, and the first instruction in that section is primed to be executed next.

This is often used to create infinite loops in your program, or finite loops if you use a conditional branch that resumes a normal execution sequence if a condition is met, like two numbers being equal or one being greater than the other.

These three action types are the minimum required to create a [[wikipedia:Turing completeness|turing complete]] computer - a computer that can calculate anything.

== Planning A Computer ==
While you might be inclined to jump head-first into building, computers are complicated things, as the previous section shows. A little bit of forethought is required before you start building in order to help guide your building decisions. Otherwise you will end up with a computer that's too messy to modify, and if it ends up malfunctioning, it'll be too messy to troubleshoot as well. '''Documentation is key'''.

Before you begin, think about what you want this computer to do. What ALU functions do you want it to have? What special instructions or special hardware? You'll also want to consider key details such as the width of your ALU, the width of your working memory and program memory, as well as the size of these memory modules, as this will determine the width of your address bus and indexing registers.

=== Example Computer ===
Since you'll likely not know what to add, this section will provide for you a very basic plan for you to follow.

==== Component Sizing ====
Our computer will be very basic. We'll be using an 8 bit ALU and 8 bit working memory. We can do a lot with 8 bits without needing to make the hardware too big.

We'll also have 256 addresses in our program memory, so an 8 bit address bus and 8 bit indexing register is in order, since 2^8 is 256. The width of the program memory is determined by our computers instruction set.

==== Instruction Set ====
This is the most influential part of planning. This will not only dictate what your computer does, but also how programs will be stored in program memory.

You can design your own instruction set from scratch if you want something more complex. But for our instruction set, we will be adding 4 types of instructions: load immediate, operate, move, and jumping/branching. These will be organized with the prefixes <code>00</code> <code>01</code> <code>10</code> and <code>11</code> respectively.

We will be squeezing our instructions into 8 bits, making our program memory 8 bits wide. With 2 of those bits being used as a prefix, that leaves 6 bits to be used as instruction arguments.

Below is the instruction set we will be using:
{| class="wikitable"
|+
!Name
!Opcode (8 bits)
!Operands
!Description
|-
|Immediate
|00 xxx xxx
|x: The immediate value.
|Puts a value given by x into register 0.
|-
|Add
|01 000___
|
|Adds the values in register 1 and 2, and puts the result in register 3.
|-
|Subtract
|01 001___
|
|Subtracts the value in register 1 from register 2 and puts the result in register 3.
|-
|And
|01 010___
|
|Bit-wise ANDs the values in register 1 and 2, and puts the result in register 3.
|-
|Or
|01 011___
|
|Bit-wise ORs the values in register 1 and 2, and puts the result in register 3.
|-
|XOR
|01 100___
|
|Bit-wise XORs the values in register 1 and 2 and puts the result in register 3.
|-
|Not
|01 101___
|
|Bit-wise NOTs the values in register 1 and 2 and puts the result in register 3.
|-
|Move
|10 xxx yyy
|x: The register to move data from. y: The register to move data to.
|Moves the data from register x into register y.
|-
|Test
|11 000___
|
|Tests the values in register 4 and 5 against each other, putting the result into the flags register.
|-
|Jump zero
|11 001___
|
|Jumps to the instruction in register 6, if the zero flag is {{On}}.
|-
|Jump carry
|11 010___
|
|Jumps to the instruction in register 6, if the carry flag is {{On}}.
|-
|Jump negative
|11 011___
|
|Jumps to the instruction in register 6, if the negative flag is {{On}}.
|-
|Jump equal
|11 100___
|
|Jumps to the instruction in register 6, if the equal flag is {{On}}.
|-
|Jump
|11 101___
|
|Jumps to the instruction in register 6, regardless of an flags.
|}
Notice that most instructions only use 3 of the 6 argument bits. Move immediate uses all 6, allowing the user to load an immediate value of 0-63, and move also uses all 6 to index 2 registers.

==== Registers ====
Since we have 3 bits available to index registers with, our computer will include 8 all-purpose registers.

If you design your own computer, you will need to consider what registers to include, and what will they be used for.

In our case, while all of our registers will be general purpose, meaning you can use them for whatever purpose you like, most of them will be used in a specific way for specific instructions. The registers and their purposes are as follows:

* Register 0 - destination for immediate values
* Register 1 - source of one argument of an operation
* Register 2 - source of the other argument of an operation
* Register 3 - destination of the result of an operation
* Register 4 - source of one argument for a comparison
* Register 5 - source of the other argument for a comparison
* Register 6 - target address for a jump
* Register 7 - general purpose

Note that the instruction pointer and instruction register are separate to these all-purpose registers, so our program will not be able to ''directly'' edit the values in these registers.

Editing of these registers is done by the control unit either during the fetch-decode-execute cycle, or through the use of a jump instruction.

==== Flags ====
If you decide to include conditional branching in your instruction set, you will need to decide what conditions (called flags) you want to check for and how you're going to check them.

In our case, we will have the following 4 flags in our computer:
* Zero flag - This flag will be {{On}} only if the first value from the last test instruction was equal to 0.
* Carry flag - This flag will be {{On}} only if that last add (or subtract) instruction carried/overflowed.
* Negative flag - This flag will be {{On}} only if the first value from the last test instruction was negative (had its most significant bit {{On}}).
* Equal flag - This flag will be {{On}} only if the values from the last test instruction were equal to each other.
We will also be storing the states of these flags in another register called a flag register. Allowing us to capture the state of these flags with one instruction (test) and use the state of these flags in another instruction (jump).

You do not need to store the state of these flags in a register, or perform a test and branch in two separate instructions. You can perform your comparison and use the results immediately, if you want. Doing so will just require a more complex execution sequence, and possibly bigger instructions.

==== Example Program ====
Putting everything together, we can use our instruction set to write a Fibonacci program:
<syntaxhighlight lang="asm">
; Initialise registers
Immediate 0 ; 00 000000
Move 2, 0 ; 10 000 010
Immediate 1 ; 00 000001
Move 1, 0 ; 10 000 001
;
; Main loop
Add ; 01 000 ___
Move 2, 1 ; 10 001 010
Move 1, 3 ; 10 011 001
Immediate 4 ; 00 000100
Move 6, 0 ; 10 000 110
Jump ; 11 101 ___
</syntaxhighlight>Visualizing the process, we can imagine the first instruction being copied into the instruction register, the instruction pointer being incremented, then the value being copied from the instruction register to register 0.

Then the step counter resets, and we begin again, fetching the instruction, incrementing the instruction counter, and moving the content of register 0 to register 2. Reset the step counter and on and on it goes.

This is what our computer ''should'' do when it's complete.

With the planning done, it's now time to move on to building.

==Building the Computer==

=== Mental Preparations ===
Depending on the size and complexity of your computer, the building phase will take several days to several months to complete. This is a full-scale project, so be aware of what you're committing to. Our example computer is simple, and should only take 1-3 days to build depending on your skill and availability. Even still, you will need to mentally prepare yourself if you're not used to working on larger scale projects. Things won't work the first time, you will need to troubleshoot things. You will learn how to do things better as you work on this, give yourself time and space to tear things down and start again if you deem it necessary. Prototypes aren't just small-scale quick-and-dirty versions of the final product that you assemble to get something done now. ''They're practice runs''. They give you the experience needed to determine what works and what doesn't. Be patient. Be willing to try when you don't know what to do, and be willing to throw it all away when you find out it doesn't work.

If you want to know what it takes to carry out a big project, the book "How Big Things Get Done" by Bent Flyvbjerg and Dan Gardner is an invaluable resource. If you read it, you might get the impression that the "correct" way to handle a project like this is to plan every little detail on paper ''before'' you start building.

'''Do not do this!'''

The key idea you should take away from this book is there are some things you just don't think about until you start putting shovels in the ground. Rather than waiting until this moment, instead try putting a spoon in a sandbox first. Do it for real, but on a smaller and cheaper scale.

Nothing is cheaper than a digital sandbox, so Logic World has you covered there. But you'll still have to build something, make your mistakes, learn, and try again. No amount of forethought will ever prepare you for what you've never tried before. Though a bit for forethought is still good practice.

=== Start With The Major Components ===
What components do you know your computer will need? What are their inputs and outputs? What do they do? These are the best places to start when building a computer.

In our example computer, we know our computer needs an 8-bit ALU. We know this ALU will have 6 functions, and we know it will produce 4 flag outputs along with the normal result output. Start by building that. Use [[Socket|sockets]] to make this component modular and to make connecting to other components easier.

We also know this computer will need registers. We'll need to be able to read from and write to these registers, but things like the ALU can also access the state of these registers directly. Building a single register with a data in/out connection, a read, write, and enable input, and a state output will allow us to duplicate the design and build our register file much faster.

We can also reuse this design for other registers like the instruction register.

The flag register, instruction pointer register, and step counter will all need to be custom built, as their behavior differs slightly from our register template. But these too are components who's inputs, outputs, and behaviors are known, and thus can quickly be built in isolation.

'''Test as you go!'''

While it may seem like extra work, you'll want to know that each component is in working order ''before'' you use them in your final build. This isn't strictly necessary, but as a general rule of thumb when building things, it '''''never''''' works right the first time. When it comes time to put everything together, it's better to only have to deal with issues that arise at that level, rather than to run around trying to fix every problem with every component at every level.

Continue to build each of the remaining components in isolation. Moving on to a small portion of [[switch]]-based program memory, and any other major components you might discover you need along the way, such as [[Multiplexer|multiplexers]], [[Decoder|decoders]], and smaller [[Lookup Table|lookup tables]] for controlling things like translating portions of the instruction register into control lines for the general purpose registers or the ALU. ''Save the control lookup table for last!'' As the inputs and outputs of this component will change as you begin to define what components you have and what their inputs/outputs are.

For example, we may discover that it'd be much easier to send a single "register read/write" line to the registers, and then use a decoder to translate bits from the instruction register into enable lines to exact fine control over the individual registers.

Or, we may discover that our lookup table needs to take the state of our flag register into account when performing certain instructions.

These are things we discover as we build, and as such, it's best to leave things like the control unit for last.

=== Putting It All Together ===
Alright! You have all your components built, and they're all working in isolation. Pat yourself on the back.

Now comes time to wire it all together.

Don't be afraid to make a mess. Remember, we haven't actually tested everything together as a whole yet. We have no idea if it will work, or if we overlooked something. Doing our fine-polishing work now if something isn't working properly will just be a waste of time and lead to frustration as we try to squeeze patches into what was once our finest masterpiece.

This is also why we built a small portion of switch-based program memory. The smaller size means we don't invest too much time building a massive component that we just don't need right now, and making it switched based will eliminate the need to reprogram our program memory every time we want to conduct a test.

You can even make multiple copies of your program memory and load different test programs on each one for a more thorough testing procedure.

Lay out all your major components as best as you can. It helps to have them surround a large open area. Use buses to make the connections, and when you feel like everything is ready, load your program memory with a small test program, start the clock and see what happens.

More than likely, things will not work as you had expected. Here's where you're going to need to slow down and troubleshoot things. Use the [[Tick|simulation controls]] to slow down, stop, and step the logic simulator. At this level, most issues you will experience are related to timing. Register inputs are not being held during the duration of a write. The ALU output is not stabilizing in time. Things like that. Though it is also possible that one of your components isn't working as it should, or its behavior needs to change in some way.

This is why we made our components modular. If this does happen, take the defective component out, fix or rebuild it, and plug it back in.

Be sure to run all of your test programs again after making a change. Sometimes changing one thing can fix one issue, and create another. Don't assume previous tests will pass just because they were passing before the change.

=== Refine and Repeat ===
Eventually, after many cycles of testing, troubleshooting, and repairing, your rough prototype will be in working order.

Congratulations! You just built your first computer!

Now comes time to polish things up, if you want to.

You can replace your test program memory modules with a full sized program memory module, if you want. Or you can begin the process of organizing your components.

Compress them down, rearrange them, stack them in a neat package. Just be sure to do it one step at a time, and test after each change.

When you're happy with how things look, you can call it done.

Again, be sure to replace your test program memory modules with a full sized module, and for easy programming/using of your computer, consider adding a programmers interface where you can punch in programs and read the state of your registers.

Whatever you do, make it yours.

Your First Computer

2025-10-17T21:36:51Z

N00basaurus: Minor update to phrasing and formatting

Your First Computer

2025-10-12T15:13:56Z

N00basaurus: /* Instruction Set */ spelling

Your First Computer

2025-10-12T15:03:31Z

N00basaurus: /* Hardware Theory */ Added a schematic diagram for a very basic control unit

File:A schematic view of a very basic control unit.png

2025-10-12T15:00:40Z

N00basaurus:

A lookup table takes in as its inputs the content of a step counter and an instruction register, and produces as its outputs various read, write, and function signals. On the clocks rising edge, the step counter is incremented. The lookup table immediately updates its outputs, reading from various components and sending function signals. The write signals do not get sent out though until the falling edge of the clock.

As this diagram suggests, the lookup table is in control of its own instruction register, and has the ability to reset the step counter. The instruction register is updated at the beginning of every instruction sequence, and the step counter is reset at the end of every instruction sequence.

Your First Computer

2025-10-12T14:27:41Z

N00basaurus: Updated the terminology used when talking about instructions. Referring to them as instructions or opcodes rather than just binary integers.

Your First Computer

2025-10-12T06:25:55Z

N00basaurus: /* Instruction Set */ clearing up an ambiguous "it"

Your First Computer

2025-10-12T06:20:58Z

N00basaurus: Major rewrite to focus more on teaching the reader what it takes to design and build your own computer, as well as teaching the reader a little more theory. With the build guide serving more as an example than instructions to follow.

Talk:Edge Detection

2025-10-12T03:15:43Z

N00basaurus: /* Edge detection circuit diagram output is not delayed */ Reply

== Edge detection circuit diagram output is not delayed ==

@[[User:N00basaurus|N00basaurus]], in the circuit diagram you show (not lw), the output immediately becomes 1 as soon as the input becomes 1, whereas in logicworld the behaviour would be a bit different, in that the output would be delayed by one tick. I'd propose delaying the output by 1 tick in the diagram to not 'bait' people into thinking they could build such a circuit even though they cannot. [[User:GHXX|GHXX]] ([[User talk:GHXX|talk]]) 18:54, 7 October 2025 (UTC)

:@[[User:GHXX|GHXX]] btw i made that diagram. I thought about it, but the article is about rising edge. The LW behavior is shown on the last screenshot.
:Maybe we can leave the screenshot alone for demonstration. And instead of the diagram make a drawing that just highlights the rising edge without considering ticks [[User:DjSapsan|DjSapsan]] ([[User talk:DjSapsan|talk]]) 15:54, 8 October 2025 (UTC)
::I added a small note explaining the diagram is simplified, and that there would be latency in a real circuit.
::Hopefully that'll act as a nice middle ground. [[User:N00basaurus|N00basaurus]] ([[User talk:N00basaurus|talk]]) 03:15, 12 October 2025 (UTC)

Edge Detection

2025-10-12T03:14:34Z

N00basaurus: Added a note below the example signal diagram explaining the lack of a delay on the output.

'''Edge detection''' is the process of sending a signal at the moment a signal transitions.

A '''rising edge''' refers to the instant when a signal changes from ''off'' to ''on''.

A '''falling edge''' refers to the instant when a signal changes from ''on'' to ''off''.

== Construction ==
[[File:Raising-edge-detector.png|thumb|right|alt=Raising edge detector|Raising edge detector]]
You can detect a rising edge by checking whether the input signal was ''off'' some number of [[Tick|ticks]] ago but is now ''on''.

This can be done using an [[AND Gate]] and an [[Inverter]].
Connect one input of the AND gate directly to your signal, and connect the other input through the inverter.

When the input signal turns on, the direct input to the AND gate is immediately on. The inverter output, however, is delayed by 1 tick, so it remains ''on'' for one more tick.
Since both inputs of the AND gate are ''on'', it becomes marked for activation in the next tick.

On the next tick, the AND gate turns ''on'' while the inverter output turns ''off''. At this point, not all AND gate inputs are ''on'', so it will be marked to turn ''off'' on the following tick.

The pulse length is determined by the delay between the direct and inverted inputs of the AND gate.
You can extend the pulse to 2 ticks using a [[Buffer]], or make it 2 ticks or longer with a [[Delayer]].

== Example Signal Diagram ==
Below is an example timing diagram showing how a rising edge detector behaves:
* '''Input''' shows the original signal toggling between off and on.
* '''Output''' is the short pulse generated on each rising edge of the input signal.

{{Binary signal
| signals=Input, Output
| signal1=000011110000111
| signal2=000010000000100
}}{{Note|NOTE: This diagram is simplified for education purposes. While this diagram suggests that the output turns on immediately when the input turns on, in reality, logic gates create a delay, and the output signal will lag the input signal by at least one tick.}}

How it looks in the Logic World:
[[File:edge-oscillator.png|frame|center|alt=oscilloscope|Raising Edge on oscilloscope ]]

User:N00basaurus

2025-10-06T06:46:33Z

N00basaurus: I made a me

I'd prefer to format it as n00b_asaurus, but MediaWiki doesn't like that ¯\_(ツ)_/¯

Anyway, hello, I'm n00b_asaurus - tinkerer, home-brew computer enthusiast, YouTuber... sorta..

[https://www.youtube.com/@n00b_asaurus My YouTube Channel].

If you've been captivated by the idea of building your own CPU from scratch, I've got a playlist on my channel that might help out.

Yes, it was technically made to help guide you through making a ''redstone'' computer, but the videos discussing topics are, for the most part, implementation-agnostic. So just skip the stuff involving redstone and it'll work all the same :P

Programmable Logic Array

2025-10-06T06:32:42Z

N00basaurus: Created a rough outline for a Programmable Logic Array page

A Programmable Logic Array, or PLA, is a combination logic component that allows you to encode any boolean expression into a simple, repeating circuit, provided the boolean expression is rearranged as a [[wikipedia:Disjunctive_normal_form|sum-of-products]] form.

{{Todo|Add a basic PLA example, explain what it's doing}}

Finite State Machine

2025-10-06T06:24:21Z

N00basaurus: Created a rough outline of a Finite State Machine page

{{Todo|The whole page}}

A Finite State Machine is a circuit that will produce a sequence of states and output signals depending on input conditions and a state graph.

It's constructed using either a [[ROM]], or a [[Programmable Logic Array]], by taking some or all of the components outputs and connecting them to some or all of its inputs through a [[Register]].

The component can then be used to create mappings of one list of states to another.

For example, you could map the states <code>1 to 2</code>, <code>2 to 3</code>, <code>3 to 5</code>, <code>5 to 8</code>, and <code>8 to 13</code>, and as you pulse the register, you will see the sequence <code>1, 2, 3, 5, 8, 13</code> appear.

Where state machines become really powerful though is when you map <code>13 to 1</code> , doing so creates a loop in the graph, and allows the sequence to repeat indefinitely.

You can have extra inputs to act as flags to check, allowing you to create conditional branches.

For example, you could map <code>3 to 5</code> if the input <code>fib</code> was on, and you could map <code>3 to 4</code> if the <code>fib</code> input was off.

{{Todo|Add details for how this condition check is actually implemented}}{{Todo|Describe how multiple condition checks in the same state are handled}}

In cases where an input is not checked, but is actually ignored, you'll need to implement the same state mapping twice, once for if the condition is on, and again for if the condition is off, in order for the transition from state to state to happen regardless of the conditions state.

This is only true if you're using a [[ROM]] to represent your state graph. If you are using a [[Programmable Logic Array]], you can just not connect the input.

A state machine can also produce extra outputs in each state.

This can be done by connecting a [[Lookup Table]] to the output of the state register, and mapping each valid state to a combination of outputs. This setup is referred to as a [[wikipedia:Moore_machine|Moore machine]].

Alternatively, you can give the state machine more outputs and synchronize them with another register. This allows the state machine to pick the next combination of outputs at the transition. This setup is referred to as a [[wikipedia:Mealy_machine|Mealy machine]].

{{Todo|Describe the advantages each machine has}}

Edge Detection

2025-10-06T05:59:51Z

N00basaurus: Added Edge Detection page

Edge detection is the action of sending a signal at the edge of a signals transition.

Rising edge refers to the instance in time when a signal ''rises'' from off to on.

Falling edge refers to the instance in time when a signal ''falls'' from on to off.

== Circuit Implementation ==
{{Todo|Add pictures}}
You can detect a rising edge by looking for an instance in time when the input signal was off some number of [[Tick|ticks]] ago, but is now on.

You can do this with an [[AND Gate]] and an [[Inverter]].

Connecting one input of the AND gate to your input signal, and another input to your input signal through an inverter.

When you turn the input signal on, the AND gates input will turn on instantly. Since the inverter has a 1 tick delay before its output is updated, its output is still on, and so is the other input of the AND gate, marking the AND gate to be updated in the next tick.

On the next tick, the AND gate turns on, and the inverter turns off. The AND gates inputs are no longer all on, and the AND gate is marked to be turned off in the next tick.

The length of this pulse is determined by the delay between the input signal and the inverted input of the AND gate. You can make the pulse length 2 ticks long by introducing a [[Buffer]], or you can make it 2 ticks or more using a [[Delayer]].
{{Todo|Add timing diagram}}

Control Unit

2025-10-06T05:47:33Z

N00basaurus: Created a rough outline for a Control Unit page

{{Todo|The whole page}}

A control unit is a composite component built for the express purpose of controlling another circuit.

In general, a control unit can do 2 things:

# provide a secured interface that prevents illegal control signal combinations from being generated.
# produce a sequence of control signal combinations over time.

In the context of computers, a control unit focuses more on this second behavior.

== Computer Control Units Abstract ==

All computers, no matter how complicated, are built on a single action: transfer state from one place to another. Sequence different forms of this action in different ways and in different combinations, and you can perform any computation.

All transfers require 1 read signal and 1 write signal. If you want to transfer the state of one [[Register]] to another, you would need to produce a signal that first enabled the read signal on one register, then enabled the write signal on the other.

A control unit is what would produce those signals in that order.

Likewise, if you wish to perform more state transfers, modify the state at some point, and use it to do something like activate a [[Display]], a control unit would be used to produce those signals in that order too.

Computer control units can often also produce different sequences of control signals depending on its inputs.

These inputs are usually connected to various parts of the computer such as the [[Instruction Register]], [[Status Register]], or other flag signals around the system.

This set up allows the control unit to "execute an instruction" by looking at the instruction register and modifying the sequence of control signals accordingly.

A control unit can also modify the state of an instruction register by bringing a new state in from somewhere else. A sequence often referred to as an instruction fetch.

In computers, every control unit will include in its sequences of operations a special sequence that first performs an instruction fetch, then queries the instruction register to determine what sequence it should produce next.

This process is referred to as the fetch, decode, execute cycle.

Typically, timing is regulated through the use of a [[Clock]].

== Computer Control Units Implementation ==

For [[Pipeline Computers]], the sequence of control signals are produced with a chain of shift registers. Each one passing its state to the next one at the [[Edge Detection|rising edge]] of the clock.

Each register represents one stage in the pipeline, and each stage produces its control signals by passing the stages state into a [[Decoder]], [[Lookup Table]], [[Programmable Logic Array]], or [[ROM]].

As new states are shifted into the stage, the control signals for that stage will change accordingly.

For all other computers, a more complex solution is often in order.

While you can get away with using a [[Counter]] and a [[ROM]], more complex sequences involving looping sequences and conditional checks is more often achieved with the use of a [[Finite State Machine]].

Decoder

2025-10-06T05:09:19Z

N00basaurus: Changed the control unit link from CU to Control Unit

; '''Decoder'''
: In ''Logic World'', a '''Decoder''' is a circuit that takes a binary input and activates one specific output bit corresponding to that input.
: It is commonly used to select one element out of many, for example a cell in memory.
: The Decoder always outputs a single bit.
: Effectively it's translating a binary value into a [[wikipedia:Unary_numeral_system|unary]] value.
: [[File:4bit-decoder.png|alt=4-bit decoder. Input on the left is 1110. The 14th output bit on the right is activated.|thumb|4-bit decoder. Input on the left is 1110. The 14th output bit on the right is activated.]]

== Construction ==

A Decoder is one of the simplest circuits to build.
First, determine how many bits you need.
The number of output bits from input bits is given by:

:<math>o = 2^i</math>

And vice versa:

:<math>i = \log_2(o)</math>

So, if you want 256 outputs, you will need a decoder with 8 input bits.
Each output has a specific pattern of {{on}} and {{off}} bits coming from the input. The circuit is basically a number of [[AND Gate|AND]] gates for each possible combination.

Here are the steps to build it:

* Place a row of input items.
* Connect each input bit to both a [[Inverter|NOT]] gate and a [[Buffer]].The NOT gate is required to have the inverted value and the Buffer is required to match the delay with the NOT gate.
* Place a row of NOT gates to serve as the outputs.
* Go through each output NOT gate and connect them to the corresponding inputs (normal or inverted) to match its binary value. For example, the output corresponding to number 12 (binary 1100) should receive the following binary values:
** 1st bit – normal
** 2nd bit – normal
** 3rd bit – inverted
** 4th bit – inverted
:and so on for each value.

You can design a decoder in different ways. If you are building one for the first time, you may want to explicitly place each wire and gate to match the real electronic analog or to be visually understandable.

When you become more experienced, you can skip unnecessary details and make it as simple as the screenshot above demonstrates. This design, optimized for speed and size, uses the trick of connecting wires from '''output''' pins directly to the required items, avoiding additional buffers and wire routing. On the screenshot below you can see the side view and how it allows it to make it compact.

[[File:Decoder-side.png|thumb|center|alt=Side view of the decoder|Side view of the decoder]]

== Speed ==

The compact design above computes the output in 2 ticks.

== Part of ==

Decoders are used primarily as part of the following circuits:

[[RAM]], [[ROM]]<br>
[[Control Unit]]<br>
[[Multiplexer]], [[Demultiplexer]]<br>
[[Lookup_Table]]<br>

== See also ==
* [[Encoder]]
* [[Lookup Table]]

Tick

2025-10-06T05:00:56Z

N00basaurus: Updated the summary to go into detail about wires transmitting signals in the same tick

{{stub}}

A '''tick''' refers to one step of the game's logic simulation.

Most [[component|components]] take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs.

It's important to note that only components introduce a tick delay. Signals traveling through [[Wiring]] are instant, no matter how long the wire is.

This is also true even if the wire sends its signal through a [[Peg]] or a [[Socket]].

If the state of a components output is updated, the connected inputs of other components will be updated in the same tick.
[[File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]

[[File:XOR gate activation delay.png|thumb|A demonstration of two XOR gates being activated. The top XOR gate has one of its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom XOR gate has had one of its inputs active for at least 1 tick, and its output is therefore active.]]

== Simulation Speed ==
While every components state is calculated and updated at each tick, the number of ticks that occur in a second can be adjusted from as low as 1 tick per second (tps) all the way up to 10,000 tps.

Adjustments can be made by opening up the simulation controls menu. By default, this is the {{keys|F9}} button.

Additionally, the simulation can be paused entirely, and stepped 1 tick at a time from the control menu. Useful for debugging circuits that don't behave like you'd expect.

You can also pause/resume the simulation or step the simulation using hotkeys on your keyboard.

By default, this is {{keys|F10}} to pause/resume the simulation, and {{keys|shift+F10}} to step the simulation when paused.
{{Todo|Add screenshots of the simulation controls menu}}

Tick

2025-09-10T20:16:55Z

N00basaurus: Added a paragraph on controlling the simulation speed

{{stub}}

A '''tick''' refers to one step of the game's logic simulation.

Most [[component|components]] take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs.
{{Todo|Add more general information about timing}}[[File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]

[[File:XOR gate activation delay.png|thumb|A demonstration of two XOR gates being activated. The top XOR gate has one of its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom XOR gate has had one of its inputs active for at least 1 tick, and its output is therefore active.]]

== Simulation Speed ==
While every components state is calculated and updated at each tick, the number of ticks that occur in a second can be adjusted from as low as 1 tick per second (tps) all the way up to 10,000 tps.

Adjustments can be made by opening up the simulation controls menu. By default, this is the <code>f9</code> button.

Additionally, the simulation can be paused entirely, and stepped 1 tick at a time from the control menu. Useful for debugging circuits that don't behave like you'd expect.

You can also pause/resume the simulation or step the simulation using hotkeys on your keyboard.

By default, this is <code>f10</code> to pause/resume the simulation, and <code>shift+f10</code> to step the simulation when paused.
{{Todo|Add screenshots of the simulation controls menu}}

Optimization

2025-09-10T20:06:35Z

N00basaurus: Linked the speed section to the tick article

== Optimization ==

There are countless ways to build any given circuit. Different designs will have different characteristics.
This article will help you design circuits optimized for specific purposes.
You can mix and match different techniques to achieve the results you want.

So, when designing a circuit you need to decide what you want to optimize for. Let's break down each optimization one by one.

Please note that, while you may be familiar with real electronics or programming, in ''Logic World'' there are certain features that are not obvious at first.
These features can be used to your advantage when optimizing circuits.

== Speed ==
Speed is the time it takes for a signal to propagate through a circuit.
In Logic World, most gates have a delay of 1 [[tick]]. The more sequential gates you have, the slower the circuit will be.
When you have cycles or feedback in your circuit, speed becomes even more critical.
In complex circuits, you can measure the speed by counting ticks from the first activation of the input to the ''final'' state on the output.

There are three major ways to cut the delays:

*Remove unnecessary gates
*Use fast gates, such as [[Relay|Relays]] or [[Fast Buffer|Fast Buffers]]
*Mods

Let's break it down further.

==== Remove unnecessary gates ====
To start, the most newbie-friendly way to optimize gates is to just remove repetitions.
For example, if you have a NOT gate followed by another NOT gate, you can just remove both of them! The same applies to other gates. Instead of placing many AND gates following one after another, make a single big AND gate with multiple inputs.

Now moving on to a more complex topic.
The first big distinction of ''Logic World'' from real life is that there are no OR gates! Instead, wires are just connected together.
This game design already removes some gates.
But the OR operation is still a necessary part of logic, even if implicitly. We still need to connect wires together.
The problem is that the wrong way may either introduce delays or lead to backpropagation.
{{Backpropagation}}
A solution to this by using fast gates will be discussed later. Here I will show a hacky way: connecting multiple wires together from '''output''' pins.
You may notice that in the screenshot on the right, the '''output''' pin from the button is connected to a lamp and then the lamp is connected to another gate.
In general, if a wire is connected between normal pins, it will allow the signal to travel everywhere. The exception is the '''output''' pin.
Wires ''coming'' out of '''output''' pins do not conduct signals backward. To use it, you need to connect all the affected items to all the related '''output''' pins individually. You can always find the output pin by its big fat size. The next screenshot below shows the correct way.
[[File:Fix-backprop.png|thumb|right|alt=Everything is connected from output pins|Everything is connected from output pins]]
If you do it correctly, you won't need additional gates to stop backpropagation.
The drawback is that it requires a direct path from all the inputs to the outputs.

----

Also, in complex circuits it becomes hard to see individual wires.
<div class="mw-collapsible mw-collapsed">
Expand to see an example<div class="mw-collapsible-content">
[[File:Toomanywires.png|center|frameless|alt=toomanywires|toomanywires]]
</div>
</div>

----

Moving on to other techniques to remove unnecessary gates.
This part will require some logic understanding. In many cases, you can improve the circuit by just using a different formula than the one you initially thought of.
And remember the lack of OR gates, some circuit variations are simply simpler.
For example, you need <math>(B \land A) \lor (B \land C)</math>, this will require 2 explicit AND gates. But you can rewrite it as <math>B \land (A \lor C)</math>.
Notice in the screenshot that a different formulation leads to a smaller circuit.
[[File:ABC-circuit.png|thumb|On the left - two explicit gates. On the right - a simple refactoring removes one gate]]
Although this simple example doesn't improve speed (because it's not sequential), this lesson still shows that you can remove unnecessary gates.

The most useful thing to know here is [[wikipedia:De Morgan's laws|De Morgan's laws]]. They allow you to rewrite common formulas from one form to another.
There could be other examples, but just remember, this part will become easier with experience and overall logic understanding.

A bit more complex technique is to use negations. This often requires a complete rethinking of the design.
But when done correctly, it can lead to a significant reduction in the number of gates, especially in very big circuits.
You need to stop thinking in terms of {{On}}/{{Off}} to enable/disable something.
For example, you can use {{Off}} to indicate the '''enabled''' state in some part. This will already remove a NOT gate from the design.
{{todo|add specific examples with negated logic}}

==== Use fast gates ====
In ''Logic World'' there are so-called fast gates, such as [[Relay|relays]] or [[Fast Buffer|fast buffers]].
These gates don't have a delay to propagate the signal. This is far from real life, but if you learn to use them correctly, they can significantly speed up your circuits.
Let's break them down.
*[[Fast Buffer]] is a simple gate that just propagates the signal from input to output without any delay. The main purpose is to avoid backpropagation. It's also useful to route wires neatly.
:The drawback is that it's very bulky, increasing the circuit size significantly.
*[[Relay]] is a gate that also propagates the signal without delay, but only if enabled. It's different from Fast Buffers in two major ways:
** It propagates signals both ways, so it can't be used to avoid backpropagation.
**Enabling it takes 1 tick, but after it's enabled, it will propagate the signal without delay.
While fast gates increase the overall number of gates, they remove delays.
So you can use Fast Buffer to replace regular [[Buffer|buffers]] and
Relays to replace [[AND Gate|AND gates]].
But remember, sometimes you still need regular Buffers to synchronize signals. Otherwise, signals coming from fast gates may not match with signals from other gates.
Please note, that extensive usage of fast gates may lead to slower performance, as all connected gates updated all at once each tick.

A notable example of a circuit with fast gates is an [[ICA|Instant Carry Adder ('''ICA''')]].

==== Mods ====
There are many mods that add complex circuits as single black boxes, and they usually take 1 tick to perform the function.
Examples: CPUs, RAMs, Displays, Keyboards, Network devices, Decoders, Buffers, etc.

== Performance ==
Even if you design a very fast circuit, it may be too big for the game to handle, especially on high tickrates, leading to lags or slower execution overall.
You may want to trade off some circuit speed for better simulation performance.
Usually it may be done by splitting the circuit into smaller parts that are activated only when needed.
The heaviest parts are usually decoders (by themselves or with RAM), HDDs, LUTs.
Let's say you have a huge decoder with 1024 outputs. In a naive design, it will activate all the gates at once, leading to a big lag spike.
How do you optimize it?
You can do it by iteratively converging on the output, using the divide and conquer approach.
For example, split the computation into two iterations:

#First iteration: a 3-bit decoder, effectively multiplexing the input between 8x parts.
#Second iteration: only one active 7-bit decoder among 8 parts, with 128 outputs.

You can divide it however you want, the main idea is to reduce the number of gates activated at once.

Next advice is especially important on servers with multiple people. Make sure all your circuits can halt. Even if it's small timer - add a switch. If you are not using a circuit, turn it off.

{{todo|expand on the topic}}

== Size ==
If you focus only on speed or performance, you may end up with a huge circuit that is hard to build and manage.
Sometimes you need to optimize purely for size.
Minimizing the size will make you avoid bulky fast gates, introduce cycles, remove parallelism, etc., often leading to slower circuits. But for some designs it may still be worth it.
We will not be focusing on designing a logic with a smaller footprint. Instead, here are ''structural'' tips that some people find useful:

*Use "round" or "hollow" designs.
*Use 1-tile stackable parts.
These "round" or "hollow" designs are made by placing supporting structures at the edges or against each other and putting logic and wiring in the middle of it. Always remember, ''Logic world'' is 3D!
This approach is extremely useful for wiring, as it allows you connect '''everything to everything'''.
Examples:
[[File:Compact-design1.png|frame|center|alt=Logic gates are only in 4 corners, all wires are inside |Logic gates are only in 4 corners, all wires are inside]]

[[File:Compact-design2.png|frame|center|alt=Logic gates are against each other|Logic gates are against each other]]

{{todo|expand on the topic}}

AND Gate

2025-09-06T22:55:05Z

N00basaurus: Updated sections to follow component standards

[[File:MHG.AndGate 512x512.png|thumb|A single AND gate]]
The '''AND gate''' is a basic digital logic component who's output will be active if '''all''' its inputs are active.

For a 2 input AND gate, it is 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.

An AND gate with 2 inputs will demonstrate the following behavior:
{| class="wikitable"
|+AND Gate Truth Table
!INPUT A
!INPUT B
!OUTPUT
|-
|LOW
|LOW
|LOW
|-
|LOW
|HIGH
|LOW
|-
|HIGH
|LOW
|LOW
|-
|HIGH
|HIGH
|HIGH
|}

== Timing ==
The AND gate's output will only be active if all of its inputs are active. This is true no matter how many inputs the AND gate has.
[[File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]
The AND gate has a latency of 1 tick, so in the instance when all inputs are active, the output will become active 1 tick later. As demonstrated in the example on the right.

== Configurability ==
Pressing the edit button on an AND gate allows you to change the number of inputs it has. You can select 2, 3, or 4 inputs.

Changing the number of inputs on an AND gate does not change its latency, but it does make the components bigger, with their width changing from 1 tile wide with 2 inputs to a little less than 2 tiles wide with 3 inputs, to 2 tiles wide with 4 inputs.

Note that when an AND gate has 3 inputs, while its width is less than 2 tiles, the component is centered on a tile, causing it to require 3 tiles of width.

Smaller components such as pegs and other 3 input AND gates can still occupy the adjacent tile. But other components that take up a full tile will need to be moved over.

AND Gate

2025-09-06T22:30:53Z

N00basaurus: Created a basic page describing the AND gate

[[File:MHG.AndGate 512x512.png|thumb|A single AND gate]]
The '''AND gate''' is a basic digital logic component who's output will be active if '''all''' its inputs are active.

For a 2 input AND gate, it is 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.

An AND gate with 2 inputs will demonstrate the following behavior:
{| class="wikitable"
|+AND Gate Truth Table
!INPUT A
!INPUT B
!OUTPUT
|-
|LOW
|LOW
|LOW
|-
|LOW
|HIGH
|LOW
|-
|HIGH
|LOW
|LOW
|-
|HIGH
|HIGH
|HIGH
|}

== Activation Latency ==
The AND gate's output will only be active if all of its inputs are active. This is true no matter how many inputs the AND gate has.
[[File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]
The AND gate has a latency of 1 tick, so in the instance when all inputs are active, the output will become active 1 tick later. As demonstrated in the example on the right.

== AND Gates with More Inputs ==
Pressing the edit button on an AND gate allows you to change the number of inputs it has. You can select 2, 3, or 4 inputs.

Changing the number of inputs on an AND gate does not change its latency, but it does make the components bigger, with their width changing from 1 tile wide with 2 inputs to a little less than 2 tiles wide with 3 inputs, to 2 tiles wide with 4 inputs.

Note that when an AND gate has 3 inputs, while its width is less than 2 tiles, the component is centered on a tile, causing it to require 3 tiles of width.

Smaller components such as pegs and other 3 input AND gates can still occupy the adjacent tile. But other components that take up a full tile will need to be moved over.

File:MHG.AndGate thumbnail render.png

2025-09-06T22:12:22Z

N00basaurus:

A render of an AND gate

File:And gate activation delay.png

2025-09-06T21:58:44Z

N00basaurus:

A demonstration of how an AND gate takes 1 tick to activate

File:And gate top-down.png

2025-09-06T21:45:58Z

N00basaurus:

An AND gate as viewed from above

File:And gate side profile.png

2025-09-06T21:45:01Z

N00basaurus:

An AND gate from the side