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	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=807</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=807"/>
		<updated>2025-12-19T04:13:24Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
[[File:Alu-8-bit.png|thumb|An 8-bit ALU with inputs A, B, !A, !B, Carry, XOR, AND, OR.]]&lt;br /&gt;
&lt;br /&gt;
{{ALU}}&lt;br /&gt;
:It may be called the &amp;quot;brains&amp;quot; of the [[CPU|central processor]].  &lt;br /&gt;
An ALU also has &amp;quot;flags&amp;quot; to keep track of different situations during computation.  &lt;br /&gt;
Operations that an ALU can perform include arithmetic operations such as addition and subtraction, as well as &#039;&#039;bitwise&#039;&#039; operations like XOR, NOR, AND, and OR.  &lt;br /&gt;
&lt;br /&gt;
The status flags it keeps track of are, for example:&lt;br /&gt;
* &#039;&#039;A = B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;gt; B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;lt; B&#039;&#039;&lt;br /&gt;
* Carry&lt;br /&gt;
* Others&lt;br /&gt;
&lt;br /&gt;
ALUs can have very different designs with varying specifications, such as bit size, possible operations, and speed. In principle, you don&#039;t need to implement every possible operation - a few operations are sufficient to make the system Turing complete - although additional operations make it more convenient and often faster. &lt;br /&gt;
&lt;br /&gt;
== Example ==&lt;br /&gt;
Below is an example of possible operations in an ALU:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Name&lt;br /&gt;
! Opcode&lt;br /&gt;
! Description&lt;br /&gt;
|-&lt;br /&gt;
| Add&lt;br /&gt;
| 000&lt;br /&gt;
| Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
| Sub&lt;br /&gt;
| 001&lt;br /&gt;
| Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
| AND&lt;br /&gt;
| 010&lt;br /&gt;
| Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
| NAND&lt;br /&gt;
| 011&lt;br /&gt;
| Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| OR&lt;br /&gt;
| 100&lt;br /&gt;
| Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
| NOR&lt;br /&gt;
| 101&lt;br /&gt;
| Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| XOR&lt;br /&gt;
| 110&lt;br /&gt;
| Outputs true if exactly one of A or B is true&lt;br /&gt;
|}&lt;br /&gt;
== ALU Designs ==&lt;br /&gt;
Their are two main alu Designs:&lt;br /&gt;
&lt;br /&gt;
* Mux Based ALU&#039;s&lt;br /&gt;
* Control Line Based ALU&#039;s&lt;br /&gt;
=== Mux Based ALU&#039;s ===&lt;br /&gt;
[[File:Muxbased alu.jpg|thumb|266x266px|Simple Mux Based ALU]]&lt;br /&gt;
Mux based ALU&#039;s uses a [[Multiplexer]] to select outputs from gates or operations&lt;br /&gt;
&lt;br /&gt;
Pros:&lt;br /&gt;
&lt;br /&gt;
* They are simple to make&lt;br /&gt;
* They are easy to understand&lt;br /&gt;
&lt;br /&gt;
Cons: &lt;br /&gt;
&lt;br /&gt;
* They take up a lot of space&lt;br /&gt;
* They are limited in operations&lt;br /&gt;
&lt;br /&gt;
=== Control Line Based ALU&#039;s ===&lt;br /&gt;
Unlike Mux Based ALU&#039;s, Control Line Based ALU&#039;s don&#039;t have a mux instead they have inputs like:&lt;br /&gt;
&lt;br /&gt;
* Carry&lt;br /&gt;
* !A&lt;br /&gt;
* !B&lt;br /&gt;
* OR&lt;br /&gt;
* XOR&lt;br /&gt;
* AND&lt;br /&gt;
* NOR&lt;br /&gt;
&lt;br /&gt;
They can do lots of operations. They don&#039;t have a sub mode input, instead you can turn on invert B (!B) and carry to preform subtraction.&lt;br /&gt;
&lt;br /&gt;
Note they don&#039;t have opcode input like mux based alus so you have to make a ROM that turns on specific pins like:&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|+&lt;br /&gt;
!Name&lt;br /&gt;
!Opcode&lt;br /&gt;
!Pins&lt;br /&gt;
!Description&lt;br /&gt;
|-&lt;br /&gt;
|Add&lt;br /&gt;
|0000&lt;br /&gt;
|None&lt;br /&gt;
|Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
|Sub&lt;br /&gt;
|0001&lt;br /&gt;
|Carry, !B&lt;br /&gt;
|Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
|AND&lt;br /&gt;
|0010&lt;br /&gt;
|AND&lt;br /&gt;
|Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
|NAND&lt;br /&gt;
|0011&lt;br /&gt;
|!A, !B, AND&lt;br /&gt;
|Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|OR&lt;br /&gt;
|0100&lt;br /&gt;
|OR&lt;br /&gt;
|Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|NOR&lt;br /&gt;
|0101&lt;br /&gt;
|!A, !B, OR&lt;br /&gt;
|Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|XOR&lt;br /&gt;
|0110&lt;br /&gt;
|XOR&lt;br /&gt;
|Outputs true if exactly one of A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|XNOR&lt;br /&gt;
|0111&lt;br /&gt;
|!A, !B, XOR&lt;br /&gt;
|Inverse of XOR Outputs true if exactly one of A or B is false&lt;br /&gt;
|-&lt;br /&gt;
|INC&lt;br /&gt;
|1000&lt;br /&gt;
|B = 1&lt;br /&gt;
|Increments A by 1&lt;br /&gt;
|-&lt;br /&gt;
|DEC&lt;br /&gt;
|1001&lt;br /&gt;
|Carry, !B, B = 1&lt;br /&gt;
|Decrements A by 1&lt;br /&gt;
|}&lt;br /&gt;
Pros: &lt;br /&gt;
&lt;br /&gt;
* They allow for complex operations.&lt;br /&gt;
* They are small&lt;br /&gt;
&lt;br /&gt;
Cons:&lt;br /&gt;
&lt;br /&gt;
* They are complex&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=806</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=806"/>
		<updated>2025-12-19T04:10:08Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: Fixed grammer mystakes.&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
[[File:Alu-8-bit.png|thumb|An 8-bit ALU with inputs A, B, !A, !B, Carry, XOR, AND, OR.]]&lt;br /&gt;
&lt;br /&gt;
{{ALU}}&lt;br /&gt;
:It may be called the &amp;quot;brains&amp;quot; of the [[CPU|central processor]].  &lt;br /&gt;
An ALU also has &amp;quot;flags&amp;quot; to keep track of different situations during computation.  &lt;br /&gt;
Operations that an ALU can perform include arithmetic operations such as addition and subtraction, as well as &#039;&#039;bitwise&#039;&#039; operations like XOR, NOR, AND, and OR.  &lt;br /&gt;
&lt;br /&gt;
The status flags it keeps track of are, for example:&lt;br /&gt;
* &#039;&#039;A = B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;gt; B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;lt; B&#039;&#039;&lt;br /&gt;
* Carry&lt;br /&gt;
* Others&lt;br /&gt;
&lt;br /&gt;
ALUs can have very different designs with varying specifications, such as bit size, possible operations, and speed. In principle, you don&#039;t need to implement every possible operation - a few operations are sufficient to make the system Turing complete - although additional operations make it more convenient and often faster. &lt;br /&gt;
&lt;br /&gt;
== Example ==&lt;br /&gt;
Below is an example of possible operations in an ALU:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Name&lt;br /&gt;
! Opcode&lt;br /&gt;
! Description&lt;br /&gt;
|-&lt;br /&gt;
| Add&lt;br /&gt;
| 000&lt;br /&gt;
| Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
| Sub&lt;br /&gt;
| 001&lt;br /&gt;
| Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
| AND&lt;br /&gt;
| 010&lt;br /&gt;
| Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
| NAND&lt;br /&gt;
| 011&lt;br /&gt;
| Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| OR&lt;br /&gt;
| 100&lt;br /&gt;
| Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
| NOR&lt;br /&gt;
| 101&lt;br /&gt;
| Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| XOR&lt;br /&gt;
| 110&lt;br /&gt;
| Outputs true if exactly one of A or B is true&lt;br /&gt;
|}&lt;br /&gt;
== ALU Designs ==&lt;br /&gt;
Their are two main alu Designs:&lt;br /&gt;
&lt;br /&gt;
* Mux Based ALU&#039;s&lt;br /&gt;
* Control Line Based ALU&#039;s&lt;br /&gt;
=== Mux Based ALU&#039;s ===&lt;br /&gt;
[[File:Muxbased alu.jpg|thumb|266x266px|Simple Mux Based ALU]]&lt;br /&gt;
Mux based ALU&#039;s uses a [[Multiplexer]] to select outputs from gates or operations&lt;br /&gt;
&lt;br /&gt;
Pros:&lt;br /&gt;
&lt;br /&gt;
* They are simple to make&lt;br /&gt;
* They are easy to understand&lt;br /&gt;
&lt;br /&gt;
Cons: &lt;br /&gt;
&lt;br /&gt;
* They take up a lot of space&lt;br /&gt;
* They are limited in operations&lt;br /&gt;
&lt;br /&gt;
=== Control Line Based ALU&#039;s ===&lt;br /&gt;
Unlike Mux Based ALU&#039;s, Control Line Based ALU&#039;s don&#039;t have a mux instead they have inputs like:&lt;br /&gt;
&lt;br /&gt;
* Carry&lt;br /&gt;
* !A&lt;br /&gt;
* !B&lt;br /&gt;
* OR&lt;br /&gt;
* XOR&lt;br /&gt;
* AND&lt;br /&gt;
* NOR&lt;br /&gt;
&lt;br /&gt;
They can do lots of operations. they don&#039;t have a sub mode input insread to subtract number you can turn on invert B (!B) and carry.&lt;br /&gt;
&lt;br /&gt;
Note they don&#039;t have opcode input like mux based alus so you have to make a ROM that turns on specific pins like:&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|+&lt;br /&gt;
!Name&lt;br /&gt;
!Opcode&lt;br /&gt;
!Pins&lt;br /&gt;
!Description&lt;br /&gt;
|-&lt;br /&gt;
|Add&lt;br /&gt;
|0000&lt;br /&gt;
|None&lt;br /&gt;
|Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
|Sub&lt;br /&gt;
|0001&lt;br /&gt;
|Carry, !B&lt;br /&gt;
|Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
|AND&lt;br /&gt;
|0010&lt;br /&gt;
|AND&lt;br /&gt;
|Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
|NAND&lt;br /&gt;
|0011&lt;br /&gt;
|!A, !B, AND&lt;br /&gt;
|Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|OR&lt;br /&gt;
|0100&lt;br /&gt;
|OR&lt;br /&gt;
|Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|NOR&lt;br /&gt;
|0101&lt;br /&gt;
|!A, !B, OR&lt;br /&gt;
|Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|XOR&lt;br /&gt;
|0110&lt;br /&gt;
|XOR&lt;br /&gt;
|Outputs true if exactly one of A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|XNOR&lt;br /&gt;
|0111&lt;br /&gt;
|!A, !B, XOR&lt;br /&gt;
|Inverse of XOR Outputs true if exactly one of A or B is false&lt;br /&gt;
|-&lt;br /&gt;
|INC&lt;br /&gt;
|1000&lt;br /&gt;
|B = 1&lt;br /&gt;
|Increments A by 1&lt;br /&gt;
|-&lt;br /&gt;
|DEC&lt;br /&gt;
|1001&lt;br /&gt;
|Carry, !B, B = 1&lt;br /&gt;
|Decrements A by 1&lt;br /&gt;
|}&lt;br /&gt;
Pros: &lt;br /&gt;
&lt;br /&gt;
* They allow for complex oprations.&lt;br /&gt;
* They are small&lt;br /&gt;
&lt;br /&gt;
Cons:&lt;br /&gt;
&lt;br /&gt;
* They are complex&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=723</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=723"/>
		<updated>2025-09-14T15:45:56Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: Fixed grammer mystakes.&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
[[File:Alu-8-bit.png|thumb|An 8-bit ALU with inputs A, B, !A, !B, Carry, XOR, AND, OR.]]&lt;br /&gt;
&lt;br /&gt;
{{ALU}}&lt;br /&gt;
:It may be called the &amp;quot;brains&amp;quot; of the [[CPU|central processor]].  &lt;br /&gt;
An ALU also has &amp;quot;flags&amp;quot; to keep track of different situations during computation.  &lt;br /&gt;
Operations that an ALU can perform include arithmetic operations such as addition and subtraction, as well as &#039;&#039;bitwise&#039;&#039; operations like XOR, NOR, AND, and OR.  &lt;br /&gt;
&lt;br /&gt;
The status flags it keeps track of are, for example:&lt;br /&gt;
* &#039;&#039;A = B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;gt; B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;lt; B&#039;&#039;&lt;br /&gt;
* Carry&lt;br /&gt;
* Others&lt;br /&gt;
&lt;br /&gt;
ALUs can have very different designs with varying specifications, such as bit size, possible operations, and speed. In principle, you don&#039;t need to implement every possible operation - a few operations are sufficient to make the system Turing complete - although additional operations make it more convenient and often faster. &lt;br /&gt;
&lt;br /&gt;
== Example ==&lt;br /&gt;
Below is an example of possible operations in an ALU:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Name&lt;br /&gt;
! Opcode&lt;br /&gt;
! Description&lt;br /&gt;
|-&lt;br /&gt;
| Add&lt;br /&gt;
| 000&lt;br /&gt;
| Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
| Sub&lt;br /&gt;
| 001&lt;br /&gt;
| Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
| AND&lt;br /&gt;
| 010&lt;br /&gt;
| Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
| NAND&lt;br /&gt;
| 011&lt;br /&gt;
| Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| OR&lt;br /&gt;
| 100&lt;br /&gt;
| Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
| NOR&lt;br /&gt;
| 101&lt;br /&gt;
| Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| XOR&lt;br /&gt;
| 110&lt;br /&gt;
| Outputs true if exactly one of A or B is true&lt;br /&gt;
|}&lt;br /&gt;
== ALU Designs ==&lt;br /&gt;
Their are two main alu Designs:&lt;br /&gt;
&lt;br /&gt;
* Mux Based ALU&#039;s&lt;br /&gt;
* Control Line Based ALU&#039;s&lt;br /&gt;
=== Mux Based ALU&#039;s ===&lt;br /&gt;
[[File:Muxbased alu.jpg|thumb|266x266px|Simple Mux Based ALU]]&lt;br /&gt;
Mux based ALU&#039;s uses a [[Multiplexer]] to select outputs from gates or oprations&lt;br /&gt;
&lt;br /&gt;
Pros:&lt;br /&gt;
&lt;br /&gt;
* They are simple to make&lt;br /&gt;
* They are easy to understand&lt;br /&gt;
&lt;br /&gt;
Cons: &lt;br /&gt;
&lt;br /&gt;
* They take up alot of space&lt;br /&gt;
* They are limited in operations&lt;br /&gt;
&lt;br /&gt;
=== Control Line Based ALU&#039;s ===&lt;br /&gt;
Unlike Mux Based ALU&#039;s, Control Line Based ALU&#039;s dont have a mux instead they have inputs like:&lt;br /&gt;
&lt;br /&gt;
* Carry&lt;br /&gt;
* !A&lt;br /&gt;
* !B&lt;br /&gt;
* OR&lt;br /&gt;
* XOR&lt;br /&gt;
* AND&lt;br /&gt;
* NOR&lt;br /&gt;
&lt;br /&gt;
They can do lots of operations. they dont have a sub mod input insread to subtract number you can turn on invert B (!B) and carry.&lt;br /&gt;
&lt;br /&gt;
Note they dont have opcode input like mux based alus so you have to make a ROM that turns on specific pins like:&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|+&lt;br /&gt;
!Name&lt;br /&gt;
!Opcode&lt;br /&gt;
!Pins&lt;br /&gt;
!Description&lt;br /&gt;
|-&lt;br /&gt;
|Add&lt;br /&gt;
|0000&lt;br /&gt;
|None&lt;br /&gt;
|Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
|Sub&lt;br /&gt;
|0001&lt;br /&gt;
|Carry, !B&lt;br /&gt;
|Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
|AND&lt;br /&gt;
|0010&lt;br /&gt;
|AND&lt;br /&gt;
|Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
|NAND&lt;br /&gt;
|0011&lt;br /&gt;
|!A, !B, AND&lt;br /&gt;
|Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|OR&lt;br /&gt;
|0100&lt;br /&gt;
|OR&lt;br /&gt;
|Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|NOR&lt;br /&gt;
|0101&lt;br /&gt;
|!A, !B, OR&lt;br /&gt;
|Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|XOR&lt;br /&gt;
|0110&lt;br /&gt;
|XOR&lt;br /&gt;
|Outputs true if exactly one of A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|XNOR&lt;br /&gt;
|0111&lt;br /&gt;
|!A, !B, XOR&lt;br /&gt;
|Inverse of XOR Outputs true if exactly one of A or B is false&lt;br /&gt;
|-&lt;br /&gt;
|INC&lt;br /&gt;
|1000&lt;br /&gt;
|B = 1&lt;br /&gt;
|Increments A by 1&lt;br /&gt;
|-&lt;br /&gt;
|DEC&lt;br /&gt;
|1001&lt;br /&gt;
|Carry, !B, B = 1&lt;br /&gt;
|Decrements A by 1&lt;br /&gt;
|}&lt;br /&gt;
Pros: &lt;br /&gt;
&lt;br /&gt;
* They allow for complex oprations.&lt;br /&gt;
* They are small&lt;br /&gt;
&lt;br /&gt;
Cons:&lt;br /&gt;
&lt;br /&gt;
* They are complex&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=721</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=721"/>
		<updated>2025-09-14T15:41:26Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: added Mux based alus and control Line based alu&amp;#039;s.&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
[[File:Alu-8-bit.png|thumb|An 8-bit ALU with inputs A, B, !A, !B, Carry, XOR, AND, OR.]]&lt;br /&gt;
&lt;br /&gt;
{{ALU}}&lt;br /&gt;
:It may be called the &amp;quot;brains&amp;quot; of the [[CPU|central processor]].  &lt;br /&gt;
An ALU also has &amp;quot;flags&amp;quot; to keep track of different situations during computation.  &lt;br /&gt;
Operations that an ALU can perform include arithmetic operations such as addition and subtraction, as well as &#039;&#039;bitwise&#039;&#039; operations like XOR, NOR, AND, and OR.  &lt;br /&gt;
&lt;br /&gt;
The status flags it keeps track of are, for example:&lt;br /&gt;
* &#039;&#039;A = B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;gt; B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;lt; B&#039;&#039;&lt;br /&gt;
* Carry&lt;br /&gt;
* Others&lt;br /&gt;
&lt;br /&gt;
ALUs can have very different designs with varying specifications, such as bit size, possible operations, and speed. In principle, you don&#039;t need to implement every possible operation - a few operations are sufficient to make the system Turing complete - although additional operations make it more convenient and often faster. &lt;br /&gt;
&lt;br /&gt;
== Example ==&lt;br /&gt;
Below is an example of possible operations in an ALU:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Name&lt;br /&gt;
! Opcode&lt;br /&gt;
! Description&lt;br /&gt;
|-&lt;br /&gt;
| Add&lt;br /&gt;
| 000&lt;br /&gt;
| Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
| Sub&lt;br /&gt;
| 001&lt;br /&gt;
| Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
| AND&lt;br /&gt;
| 010&lt;br /&gt;
| Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
| NAND&lt;br /&gt;
| 011&lt;br /&gt;
| Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| OR&lt;br /&gt;
| 100&lt;br /&gt;
| Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
| NOR&lt;br /&gt;
| 101&lt;br /&gt;
| Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| XOR&lt;br /&gt;
| 110&lt;br /&gt;
| Outputs true if exactly one of A or B is true&lt;br /&gt;
|}&lt;br /&gt;
== ALU Designs ==&lt;br /&gt;
Their are two main alu Designs:&lt;br /&gt;
&lt;br /&gt;
* Mux Based ALU&#039;s&lt;br /&gt;
* Control Line Based ALU&#039;s&lt;br /&gt;
=== Mux Based ALU&#039;s ===&lt;br /&gt;
[[File:Muxbased alu.jpg|thumb|266x266px|Simple Mux Based ALU]]&lt;br /&gt;
Mux based ALU&#039;s uses a [[Multiplexer]] to select outputs from gates or oprations&lt;br /&gt;
Pros:&lt;br /&gt;
&lt;br /&gt;
* They are simple to make&lt;br /&gt;
* They are easy to understand&lt;br /&gt;
&lt;br /&gt;
Cons: &lt;br /&gt;
&lt;br /&gt;
* They take up alot of space&lt;br /&gt;
* They are limited in oprations&lt;br /&gt;
&lt;br /&gt;
=== Control Line Based ALU&#039;s ===&lt;br /&gt;
Unlike Mux Based ALU&#039;s, Control Line Based ALU&#039;s dont have a mux instead they have inputs like:&lt;br /&gt;
&lt;br /&gt;
* Carry&lt;br /&gt;
* !A&lt;br /&gt;
* !B&lt;br /&gt;
* OR&lt;br /&gt;
* XOR&lt;br /&gt;
* AND&lt;br /&gt;
* NOR&lt;br /&gt;
&lt;br /&gt;
They can do lots of oprations. they dont have a sub mod input insread to subtract number you can turn on invert B (!B) and carry.&lt;br /&gt;
&lt;br /&gt;
Note they dont have opcode input like mux based alus so you have to make a ROM that turns on specific pins like:&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|+&lt;br /&gt;
!Name&lt;br /&gt;
!Opcode&lt;br /&gt;
!Pins&lt;br /&gt;
!Description&lt;br /&gt;
|-&lt;br /&gt;
|Add&lt;br /&gt;
|0000&lt;br /&gt;
|None&lt;br /&gt;
|Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
|Sub&lt;br /&gt;
|0001&lt;br /&gt;
|Carry, !B&lt;br /&gt;
|Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
|AND&lt;br /&gt;
|0010&lt;br /&gt;
|AND&lt;br /&gt;
|Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
|NAND&lt;br /&gt;
|0011&lt;br /&gt;
|!A, !B, AND&lt;br /&gt;
|Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|OR&lt;br /&gt;
|0100&lt;br /&gt;
|OR&lt;br /&gt;
|Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|NOR&lt;br /&gt;
|0101&lt;br /&gt;
|!A, !B, OR&lt;br /&gt;
|Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
|XOR&lt;br /&gt;
|0110&lt;br /&gt;
|XOR&lt;br /&gt;
|Outputs true if exactly one of A or B is true&lt;br /&gt;
|-&lt;br /&gt;
|XNOR&lt;br /&gt;
|0111&lt;br /&gt;
|!A, !B, XOR&lt;br /&gt;
|Inverse of XOR Outputs true if exactly one of A or B is false&lt;br /&gt;
|-&lt;br /&gt;
|INC&lt;br /&gt;
|1000&lt;br /&gt;
|B = 1&lt;br /&gt;
|Increments A by 1&lt;br /&gt;
|-&lt;br /&gt;
|DEC&lt;br /&gt;
|1001&lt;br /&gt;
|Carry, !B, B = 1&lt;br /&gt;
|Decrements A by 1&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=File:Muxbased_alu.jpg&amp;diff=718</id>
		<title>File:Muxbased alu.jpg</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=File:Muxbased_alu.jpg&amp;diff=718"/>
		<updated>2025-09-14T15:21:08Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;Simple diagram of a mux based alu.&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=717</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=717"/>
		<updated>2025-09-14T15:15:38Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: /* ALU Designs */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
[[File:Alu-8-bit.png|thumb|An 8-bit ALU with inputs A, B, !A, !B, Carry, XOR, AND, OR.]]&lt;br /&gt;
&lt;br /&gt;
{{ALU}}&lt;br /&gt;
:It may be called the &amp;quot;brains&amp;quot; of the [[CPU|central processor]].  &lt;br /&gt;
An ALU also has &amp;quot;flags&amp;quot; to keep track of different situations during computation.  &lt;br /&gt;
Operations that an ALU can perform include arithmetic operations such as addition and subtraction, as well as &#039;&#039;bitwise&#039;&#039; operations like XOR, NOR, AND, and OR.  &lt;br /&gt;
&lt;br /&gt;
The status flags it keeps track of are, for example:&lt;br /&gt;
* &#039;&#039;A = B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;gt; B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;lt; B&#039;&#039;&lt;br /&gt;
* Carry&lt;br /&gt;
* Others&lt;br /&gt;
&lt;br /&gt;
ALUs can have very different designs with varying specifications, such as bit size, possible operations, and speed. In principle, you don&#039;t need to implement every possible operation - a few operations are sufficient to make the system Turing complete - although additional operations make it more convenient and often faster. &lt;br /&gt;
&lt;br /&gt;
== Example ==&lt;br /&gt;
Below is an example of possible operations in an ALU:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Name&lt;br /&gt;
! Opcode&lt;br /&gt;
! Description&lt;br /&gt;
|-&lt;br /&gt;
| Add&lt;br /&gt;
| 000&lt;br /&gt;
| Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
| Sub&lt;br /&gt;
| 001&lt;br /&gt;
| Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
| AND&lt;br /&gt;
| 010&lt;br /&gt;
| Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
| NAND&lt;br /&gt;
| 011&lt;br /&gt;
| Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| OR&lt;br /&gt;
| 100&lt;br /&gt;
| Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
| NOR&lt;br /&gt;
| 101&lt;br /&gt;
| Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| XOR&lt;br /&gt;
| 110&lt;br /&gt;
| Outputs true if exactly one of A or B is true&lt;br /&gt;
|}&lt;br /&gt;
== ALU Designs ==&lt;br /&gt;
Their are two main alu Designs:&lt;br /&gt;
&lt;br /&gt;
* Mux Based ALU&#039;s&lt;br /&gt;
* Control Line based ALU&#039;s&lt;br /&gt;
[[Multiplexer|Multiplexer]]&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=714</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=714"/>
		<updated>2025-09-14T15:10:28Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
[[File:Alu-8-bit.png|thumb|An 8-bit ALU with inputs A, B, !A, !B, Carry, XOR, AND, OR.]]&lt;br /&gt;
&lt;br /&gt;
{{ALU}}&lt;br /&gt;
:It may be called the &amp;quot;brains&amp;quot; of the [[CPU|central processor]].  &lt;br /&gt;
An ALU also has &amp;quot;flags&amp;quot; to keep track of different situations during computation.  &lt;br /&gt;
Operations that an ALU can perform include arithmetic operations such as addition and subtraction, as well as &#039;&#039;bitwise&#039;&#039; operations like XOR, NOR, AND, and OR.  &lt;br /&gt;
&lt;br /&gt;
The status flags it keeps track of are, for example:&lt;br /&gt;
* &#039;&#039;A = B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;gt; B&#039;&#039;&lt;br /&gt;
* &#039;&#039;A &amp;lt; B&#039;&#039;&lt;br /&gt;
* Carry&lt;br /&gt;
* Others&lt;br /&gt;
&lt;br /&gt;
ALUs can have very different designs with varying specifications, such as bit size, possible operations, and speed. In principle, you don&#039;t need to implement every possible operation - a few operations are sufficient to make the system Turing complete - although additional operations make it more convenient and often faster. &lt;br /&gt;
&lt;br /&gt;
== Example ==&lt;br /&gt;
Below is an example of possible operations in an ALU:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Name&lt;br /&gt;
! Opcode&lt;br /&gt;
! Description&lt;br /&gt;
|-&lt;br /&gt;
| Add&lt;br /&gt;
| 000&lt;br /&gt;
| Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
| Sub&lt;br /&gt;
| 001&lt;br /&gt;
| Subtracts B from A&lt;br /&gt;
|-&lt;br /&gt;
| AND&lt;br /&gt;
| 010&lt;br /&gt;
| Outputs true if both A and B are true, otherwise false&lt;br /&gt;
|-&lt;br /&gt;
| NAND&lt;br /&gt;
| 011&lt;br /&gt;
| Inverse of AND. If A and B are true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| OR&lt;br /&gt;
| 100&lt;br /&gt;
| Outputs true if either A or B is true&lt;br /&gt;
|-&lt;br /&gt;
| NOR&lt;br /&gt;
| 101&lt;br /&gt;
| Inverse of OR. If either A or B is true, output is false&lt;br /&gt;
|-&lt;br /&gt;
| XOR&lt;br /&gt;
| 110&lt;br /&gt;
| Outputs true if exactly one of A or B is true&lt;br /&gt;
|}&lt;br /&gt;
== ALU Designs ==&lt;br /&gt;
Their are two main alu Designs:&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=707</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=707"/>
		<updated>2025-09-14T13:46:55Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: added the alu example. :3&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
[[File:Alu-8-bit.png|thumb|This is what a control line alu looks like it has inputs A and B, !A, !B, Carry, XOR, AND, OR.]]&lt;br /&gt;
The ALU is a component in a computer that does the actal processing in a computer, it has an opcode input and inputs for A and B. Its like the brains of the computer. It can add two numbers or subtract two numbers. It can also do bitwise operations. Like XOR, NOR, AND, OR, is 0, is -, carry. It can do flags like A = B, A &amp;gt; B, A &amp;lt; B.&lt;br /&gt;
&lt;br /&gt;
Example of what opcodes may look like:&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|+&lt;br /&gt;
!Name&lt;br /&gt;
!Opcode&lt;br /&gt;
!&#039;&#039;&#039;Description&#039;&#039;&#039;&lt;br /&gt;
|-&lt;br /&gt;
|Add&lt;br /&gt;
|000&lt;br /&gt;
|Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
|Sub&lt;br /&gt;
|001&lt;br /&gt;
|Subtracts A and B&lt;br /&gt;
|-&lt;br /&gt;
|AND&lt;br /&gt;
|010&lt;br /&gt;
|if A and B are true then output true else output false&lt;br /&gt;
|-&lt;br /&gt;
|NAND&lt;br /&gt;
|011&lt;br /&gt;
|invert of AND if A and B is true then output false&lt;br /&gt;
|-&lt;br /&gt;
|OR&lt;br /&gt;
|100&lt;br /&gt;
|either A or B&lt;br /&gt;
|-&lt;br /&gt;
|NOR&lt;br /&gt;
|101&lt;br /&gt;
|invert of OR&lt;br /&gt;
|-&lt;br /&gt;
|XOR&lt;br /&gt;
|110&lt;br /&gt;
|OR of A and B but if both are true then output false&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=File:Alu-8-bit.png&amp;diff=706</id>
		<title>File:Alu-8-bit.png</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=File:Alu-8-bit.png&amp;diff=706"/>
		<updated>2025-09-14T13:44:38Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;This is what a control line based alu looks like.&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=705</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=705"/>
		<updated>2025-09-14T13:42:28Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: Fixed grammer mystakes.&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU. The arrows represent inputs and outputs.]]&lt;br /&gt;
The ALU is a component in a computer that does the actal processing in a computer, it has an opcode input and inputs for A and B. Its like the brains of the computer. It can add two numbers or subtract two numbers. It can also do bitwise operations. Like XOR, NOR, AND, OR, is 0, is -, carry. It can do flags like A = B, A &amp;gt; B, A &amp;lt; B.&lt;br /&gt;
&lt;br /&gt;
Example of what opcodes may look like:&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|+&lt;br /&gt;
!Name&lt;br /&gt;
!Opcode&lt;br /&gt;
!&#039;&#039;&#039;Description&#039;&#039;&#039;&lt;br /&gt;
|-&lt;br /&gt;
|Add&lt;br /&gt;
|000&lt;br /&gt;
|Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
|Sub&lt;br /&gt;
|001&lt;br /&gt;
|Subtracts A and B&lt;br /&gt;
|-&lt;br /&gt;
|AND&lt;br /&gt;
|010&lt;br /&gt;
|if A and B are true then output true else output false&lt;br /&gt;
|-&lt;br /&gt;
|NAND&lt;br /&gt;
|011&lt;br /&gt;
|invert of AND if A and B is true then output false&lt;br /&gt;
|-&lt;br /&gt;
|OR&lt;br /&gt;
|100&lt;br /&gt;
|either A or B&lt;br /&gt;
|-&lt;br /&gt;
|NOR&lt;br /&gt;
|101&lt;br /&gt;
|invert of OR&lt;br /&gt;
|-&lt;br /&gt;
|XOR&lt;br /&gt;
|110&lt;br /&gt;
|OR of A and B but if both are true then output false&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=704</id>
		<title>Arithmetic logic unit</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=Arithmetic_logic_unit&amp;diff=704"/>
		<updated>2025-09-14T13:40:49Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: I added some basic explainations about the alu im going to add more stuff in this page in the future&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[File:ALU.gif|thumb|A symbolic representation of an ALU.The arrows represent inputs and outputs.]]&lt;br /&gt;
The alu is a component in a computer that does the actal processing in a computer, it has an opcode input and inputs for A and B. Its like the brains of the computer. It can add two numbers or subtract two numbers. It can also do bitwise operations. Like XOR, NOR, AND, OR, is 0, is -, carry. It can do flags like A = B, A &amp;gt; B, A &amp;lt; B.&lt;br /&gt;
&lt;br /&gt;
Example of what opcodes may look like:&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|+&lt;br /&gt;
!Name&lt;br /&gt;
!Opcode&lt;br /&gt;
!&#039;&#039;&#039;Description&#039;&#039;&#039;&lt;br /&gt;
|-&lt;br /&gt;
|Add&lt;br /&gt;
|000&lt;br /&gt;
|Adds A and B&lt;br /&gt;
|-&lt;br /&gt;
|Sub&lt;br /&gt;
|001&lt;br /&gt;
|Subtracts A and B&lt;br /&gt;
|-&lt;br /&gt;
|AND&lt;br /&gt;
|010&lt;br /&gt;
|if A and B are true then output true else output false&lt;br /&gt;
|-&lt;br /&gt;
|NAND&lt;br /&gt;
|011&lt;br /&gt;
|invert of AND if A and B is true then output false&lt;br /&gt;
|-&lt;br /&gt;
|OR&lt;br /&gt;
|100&lt;br /&gt;
|either A or B&lt;br /&gt;
|-&lt;br /&gt;
|NOR&lt;br /&gt;
|101&lt;br /&gt;
|invert of OR&lt;br /&gt;
|-&lt;br /&gt;
|XOR&lt;br /&gt;
|110&lt;br /&gt;
|OR of A and B but if both are true then output false&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
	<entry>
		<id>https://wiki.logic.world/index.php?title=File:ALU.gif&amp;diff=698</id>
		<title>File:ALU.gif</title>
		<link rel="alternate" type="text/html" href="https://wiki.logic.world/index.php?title=File:ALU.gif&amp;diff=698"/>
		<updated>2025-09-14T13:26:20Z</updated>

		<summary type="html">&lt;p&gt;Rgjava: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;A symbolic representation of an ALU.&lt;/div&gt;</summary>
		<author><name>Rgjava</name></author>
	</entry>
</feed>