AND Gate - Revision history

Jimmy at 22:53, 8 September 2025

2025-09-08T22:53:33Z

← Older revision		Revision as of 22:53, 8 September 2025
Line 55:		Line 55:
	== Placement ==		== Placement ==

	AND Gates with 2 or 3 inputs can be placed in the center of a [[Circuit Board~~\|board~~]] square or on top of a [[Mount]], and can be fine-rotated.		AND Gates with 2 or 3 inputs can be placed in the center of a [[Circuit Board]] square or on top of a [[Mount]], and can be fine-rotated.

	AND Gates with 4 inputs (or more, if the game is modified to allow more inputs) have multiple attachment points, one for each square covered by the body of the component, and cannot be fine-rotated.		AND Gates with 4 inputs (or more, if the game is modified to allow more inputs) have multiple attachment points, one for each square covered by the body of the component, and cannot be fine-rotated.

Jimmy at 22:06, 8 September 2025

2025-09-08T22:06:25Z

← Older revision		Revision as of 22:06, 8 September 2025
Line 42:		Line 42:

	The AND Gate takes one [[tick]] to update the state of its output after a change to the state of its inputs.		The AND Gate takes one [[tick]] to update the state of its output after a change to the state of its inputs.


	== Configurability ==		== Configurability ==
Line 53:		Line 52:

	The game can be modified to allow AND Gates with an unlimited number of inputs. {{todo\|details of how to do this}} {{todo\|image of an AND Gates with >4 inputs}}		The game can be modified to allow AND Gates with an unlimited number of inputs. {{todo\|details of how to do this}} {{todo\|image of an AND Gates with >4 inputs}}


	== Placement ==		== Placement ==
Line 62:		Line 60:

	{{todo\|image of different ways AND Gates can be placed}}		{{todo\|image of different ways AND Gates can be placed}}


	{{Navbox components}}		{{Navbox components}}

Jimmy at 22:04, 8 September 2025

2025-09-08T22:04:49Z

← Older revision		Revision as of 22:04, 8 September 2025
Line 14:		Line 14:
	An AND Gate with two inputs [[Measurements\|measures]] 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.		An AND Gate with two inputs [[Measurements\|measures]] 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.

	== ~~Logic~~ ==		== Behavior ==
	The AND Gate's output will only be active if all of its inputs are {{on}}. This is true no matter how many inputs the AND gate has.		The AND Gate's output will only be active if all of its inputs are {{on}}. This is true no matter how many inputs the AND gate has.

Jimmy: Overhaul to new standard component page format

2025-09-08T22:04:37Z

Overhaul to new standard component page format

← Older revision		Revision as of 22:04, 8 September 2025
Line 10:		Line 10:
	}}		}}

	The '''AND ~~gate~~''' is a ~~basic~~ digital logic ~~component whose~~ output will be {{on}} if '''all''' ~~its~~ inputs are {{on}}.		The '''AND Gate''' is a [[component]] used for [[digital logic]]. The AND Gate has one output and 2 to 4 inputs. The output will be {{on}} if and only if '''all''' of the inputs are {{on}}.

	~~For a 2 input~~ AND ~~gate, it is~~ 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.		An AND Gate with two inputs [[Measurements\|measures]] 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.

	== Logic ==		== Logic ==
	The AND ~~gate~~'s output will only be active if all of its inputs are {{on}}. This is true no matter how many inputs the AND gate has.		The AND Gate's output will only be active if all of its inputs are {{on}}. This is true no matter how many inputs the AND gate has.

	<tabber>		<tabber>
Line 41:		Line 41:
	</tabber>		</tabber>

	~~== Timing ==~~		The AND Gate takes one [[tick]] to update the state of its output after a change to the state of its inputs.
	[[~~File:And gate activation delay.png\|thumb\|A demonstration~~ of ~~two AND gates being activated. The top AND gate has both its inputs active, but~~ its output ~~is not yet active because~~ a ~~delay~~ of ~~1 tick has not yet passed. The bottom AND gate has had both~~ its inputs ~~active for at least 1 tick, and its output is therefore active~~.]]
	~~The AND gate has a latency of 1 tick, so in the instance when all inputs are {{on}}, the output will become active 1 tick later. As demonstrated in the example on the right.~~

	== Configurability ==		== Configurability ==
	~~Pressing the edit button on an AND gate allows you to change the number of inputs it has. You can select 2, 3, or 4 inputs.~~

	Changing the number of inputs on an AND ~~gate~~ does not change its latency, but it does make the components bigger, with their width changing from 1 tile wide with 2 inputs to a little less than 2 tiles wide with 3 inputs, to 2 tiles wide with 4 inputs.		Pressing the edit button on an AND Gate allows you to change the number of inputs it has. You can select 2, 3, or 4 inputs.

			Changing the number of inputs on an AND Gate does not change its latency, but it does make the components bigger, with their width changing from 1 tile wide with 2 inputs to a little less than 2 tiles wide with 3 inputs, to 2 tiles wide with 4 inputs.

			{{todo\|image of the menu for editing AND Gates and the 3 vanilla varieties}}

			The game can be modified to allow AND Gates with an unlimited number of inputs. {{todo\|details of how to do this}} {{todo\|image of an AND Gates with >4 inputs}}


			== Placement ==

			AND Gates with 2 or 3 inputs can be placed in the center of a [[Circuit Board\|board]] square or on top of a [[Mount]], and can be fine-rotated.

			AND Gates with 4 inputs (or more, if the game is modified to allow more inputs) have multiple attachment points, one for each square covered by the body of the component, and cannot be fine-rotated.

	~~Note that when an~~ AND ~~gate has 3 inputs, while its width is less than 2 tiles, the component is centered on a tile, causing it to require 3 tiles of width.~~		{{todo\|image of different ways AND Gates can be placed}}

	~~Smaller components such as pegs and other 3 input AND gates can still occupy the adjacent tile. But other components that take up a full tile will need to be moved over.~~

	{{Navbox components}}		{{Navbox components}}

Felipe: use algebraic formula

2025-09-08T16:18:44Z

use algebraic formula

← Older revision		Revision as of 16:18, 8 September 2025
Line 23:		Line 23:
	\| outputs=1		\| outputs=1
	\| caption=AND Gate Truth Table (2 inputs)		\| caption=AND Gate Truth Table (2 inputs)
	\| expr1=a b &		\| expr1=a & b
	}}		}}
	\|-\|3 Inputs=		\|-\|3 Inputs=
Line 30:		Line 30:
	\| outputs=1		\| outputs=1
	\| caption=AND Gate Truth Table (3 inputs)		\| caption=AND Gate Truth Table (3 inputs)
	\| expr1=a b c ~~& &~~		\| expr1=a & b & c
	}}		}}
	\|-\|4 Inputs=		\|-\|4 Inputs=
Line 37:		Line 37:
	\| outputs=1		\| outputs=1
	\| caption=AND Gate Truth Table (4 inputs)		\| caption=AND Gate Truth Table (4 inputs)
	\| expr1=a b c d ~~& & &~~		\| expr1=a & b & c & d
	}}		}}
	</tabber>		</tabber>

Felipe: use auto truth table

2025-09-08T12:05:38Z

use auto truth table

← Older revision		Revision as of 12:05, 8 September 2025
Line 19:		Line 19:
	<tabber>		<tabber>
	\|-\|2 Inputs=		\|-\|2 Inputs=
	{{Truth table		{{Truth table auto
	\| inputs=2		\| inputs=2
	\| outputs=1		\| outputs=1
	\| caption=AND Gate Truth Table (2 inputs)		\| caption=AND Gate Truth Table (2 inputs)
	\| ~~0 0 0~~		\| expr1=a b &
	~~\| 0 1 0~~
	~~\| 1 0 0~~
	~~\| 1 1 1~~
	}}		}}
	\|-\|3 Inputs=		\|-\|3 Inputs=
	{{Truth table		{{Truth table auto
	\| inputs=3		\| inputs=3
	\| outputs=1		\| outputs=1
	\| caption=AND Gate Truth Table (3 inputs)		\| caption=AND Gate Truth Table (3 inputs)
	\| ~~0 0 0 0~~		\| expr1=a b c & &
	~~\| 0 0 1 0~~
	~~\| 0 1 0 0~~
	~~\| 0 1 1 0~~
	~~\| 1 0 0 0~~
	~~\| 1 0 1 0~~
	~~\| 1 1 0 0~~
	~~\| 1 1 1 1~~
	}}		}}
	\|-\|4 Inputs=		\|-\|4 Inputs=
	{{Truth table		{{Truth table auto
	\| inputs=4		\| inputs=4
	\| outputs=1		\| outputs=1
	\| caption=AND Gate Truth Table (4 inputs)		\| caption=AND Gate Truth Table (4 inputs)
	\| ~~0 0 0 0 0~~		\| expr1=a b c d & & &
	~~\| 0 0 0 1 0~~
	~~\| 0 0 1 0 0~~
	~~\| 0 0 1 1 0~~
	~~\| 0 1 0 0 0~~
	~~\| 0 1 0 1 0~~
	~~\| 0 1 1 0 0~~
	~~\| 0 1 1 1 0~~
	~~\| 1 0 0 0 0~~
	~~\| 1 0 0 1 0~~
	~~\| 1 0 1 0 0~~
	~~\| 1 0 1 1 0~~
	~~\| 1 1 0 0 0~~
	~~\| 1 1 0 1 0~~
	~~\| 1 1 1 0 0~~
	~~\| 1 1 1 1 1~~
	}}		}}
	</tabber>		</tabber>

Felipe: add components navbox

2025-09-08T00:58:32Z

add components navbox

← Older revision		Revision as of 00:58, 8 September 2025
Line 78:		Line 78:

	Smaller components such as pegs and other 3 input AND gates can still occupy the adjacent tile. But other components that take up a full tile will need to be moved over.		Smaller components such as pegs and other 3 input AND gates can still occupy the adjacent tile. But other components that take up a full tile will need to be moved over.

			{{Navbox components}}

	[[Category:Vanilla components]]		[[Category:Vanilla components]]
	[[Category:Circuitry components]]		[[Category:Circuitry components]]

Jimmy: Add multiple truth tables using tabs

2025-09-07T17:57:53Z

Add multiple truth tables using tabs

@@ Line 14: / Line 14: @@
 For a 2 input AND gate, it is 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.
-An AND gate with 2 inputs will demonstrate the following behavior:
+== Logic ==
 {{Truth table
 | inputs=2
 | outputs=1
-| caption=AND Gate Truth Table
+| caption=AND Gate Truth Table (2 inputs)
 | 0 0 0
 | 0 1 0
@@ Line 25: / Line 28: @@
 | 1 1 1
 }}
 == Timing ==
 [[File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]
 The AND gate has a latency of 1 tick, so in the instance when all inputs are {{on}}, the output will become active 1 tick later. As demonstrated in the example on the right.

Felipe: use on and off templates

2025-09-07T16:48:01Z

use on and off templates

← Older revision		Revision as of 16:48, 7 September 2025
Line 10:		Line 10:
	}}		}}

	The '''AND gate''' is a basic digital logic component whose output will be ~~active~~ if '''all''' its inputs are ~~active~~.		The '''AND gate''' is a basic digital logic component whose output will be {{on}} if '''all''' its inputs are {{on}}.

	For a 2 input AND gate, it is 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.		For a 2 input AND gate, it is 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.
Line 27:		Line 27:

	== Timing ==		== Timing ==
	The AND gate's output will only be active if all of its inputs are ~~active~~. This is true no matter how many inputs the AND gate has.		The AND gate's output will only be active if all of its inputs are {{on}}. This is true no matter how many inputs the AND gate has.
	[[File:And gate activation delay.png\|thumb\|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]		[[File:And gate activation delay.png\|thumb\|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]
	The AND gate has a latency of 1 tick, so in the instance when all inputs are ~~active~~, the output will become active 1 tick later. As demonstrated in the example on the right.		The AND gate has a latency of 1 tick, so in the instance when all inputs are {{on}}, the output will become active 1 tick later. As demonstrated in the example on the right.

	== Configurability ==		== Configurability ==

Felipe: fix wording

2025-09-07T11:24:31Z

fix wording

← Older revision		Revision as of 11:24, 7 September 2025
Line 10:		Line 10:
	}}		}}

	The '''AND gate''' is a basic digital logic component ~~who's~~ output will be active if '''all''' its inputs are active.		The '''AND gate''' is a basic digital logic component whose output will be active if '''all''' its inputs are active.

	For a 2 input AND gate, it is 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.		For a 2 input AND gate, it is 1 tile wide and 1 tile tall, and its body is 1 tile long, but its inputs and outputs extend its area to 3 tiles.