Inverter Logic Gates - Revision history

FoxFireFive at 21:23, 7 September 2025

2025-09-07T21:23:21Z

← Older revision		Revision as of 21:23, 7 September 2025
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	== Inverter XOR Gate ==		== Inverter XOR Gate ==
	[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|~~115x115px~~]]		[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|172x172px]]
	An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.		An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.

FoxFireFive at 21:22, 7 September 2025

2025-09-07T21:22:58Z

← Older revision		Revision as of 21:22, 7 September 2025
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	== Inverter XOR Gate ==		== Inverter XOR Gate ==
	[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|~~287x287px~~]]		[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|115x115px]]
	An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.		An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.

FoxFireFive at 21:22, 7 September 2025

2025-09-07T21:22:46Z

← Older revision		Revision as of 21:22, 7 September 2025
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	== Inverter XOR Gate ==		== Inverter XOR Gate ==
	[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|~~172x172px~~]]		[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|287x287px]]
	An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.		An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.

FoxFireFive at 21:22, 7 September 2025

2025-09-07T21:22:04Z

← Older revision		Revision as of 21:22, 7 September 2025
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	== Inverter XOR Gate ==		== Inverter XOR Gate ==
	[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|~~229x229px~~]]		[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|172x172px]]
	An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.		An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.

FoxFireFive at 21:21, 7 September 2025

2025-09-07T21:21:32Z

← Older revision		Revision as of 21:21, 7 September 2025
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	== Inverter AND Gate ==		== Inverter AND Gate ==
	[[File:Inverter AND.jpg\|thumb\|[[AND Gate]]\|~~240x240px~~]]		[[File:Inverter AND.jpg\|thumb\|[[AND Gate]]\|200x200px]]
	An '''AND gate''' is a basic digital logic component whose output will be '''ON''' if '''all''' its inputs are '''ON'''.		An '''AND gate''' is a basic digital logic component whose output will be '''ON''' if '''all''' its inputs are '''ON'''.

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	== Inverter OR Gate ==		== Inverter OR Gate ==
	[[File:Inverter OR (Updated).jpg\|thumb\|[[OR Gate]]\|~~200x200px~~]]		[[File:Inverter OR (Updated).jpg\|thumb\|[[OR Gate]]\|235x235px]]
	An '''OR Gate''' is a basic digital logic component whose output will be '''ON''' if '''any''' of its inputs are '''ON'''.		An '''OR Gate''' is a basic digital logic component whose output will be '''ON''' if '''any''' of its inputs are '''ON'''.

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	== Inverter XOR Gate ==		== Inverter XOR Gate ==
	[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|~~200x200px~~]]		[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|229x229px]]
	An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.		An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.

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	== Inverter NAND Gate ==		== Inverter NAND Gate ==
	[[File:Inverter NAND.jpg\|thumb\|[[NAND Gate]]\|~~241x241px~~]]		[[File:Inverter NAND.jpg\|thumb\|[[NAND Gate]]\|200x200px]]
	A '''NAND gate''' is a basic digital logic component whose output will be '''OFF''' if '''all''' its inputs are '''ON'''.		A '''NAND gate''' is a basic digital logic component whose output will be '''OFF''' if '''all''' its inputs are '''ON'''.

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	== Inverter NOR Gate ==		== Inverter NOR Gate ==
	[[File:Inverter NOR.jpg\|thumb\|[[NOR Gate]]\|~~200x200px~~]]		[[File:Inverter NOR.jpg\|thumb\|[[NOR Gate]]\|222x222px]]
	A '''NOR Gate''' is a basic digital logic component whose output will be '''OFF''' if '''any''' of its inputs are '''ON'''.		A '''NOR Gate''' is a basic digital logic component whose output will be '''OFF''' if '''any''' of its inputs are '''ON'''.

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	== Inverter XNOR Gate ==		== Inverter XNOR Gate ==
	[[File:Inverter XNOR.jpg\|thumb\|[[XNOR Gate]]\|~~200x200px~~]]		[[File:Inverter XNOR.jpg\|thumb\|[[XNOR Gate]]\|275x275px]]
	An '''XNOR Gate''' is a basic digital logic component whose output will be '''ON''' if all inputs are the same.		An '''XNOR Gate''' is a basic digital logic component whose output will be '''ON''' if all inputs are the same.

FoxFireFive at 21:20, 7 September 2025

2025-09-07T21:20:37Z

← Older revision		Revision as of 21:20, 7 September 2025
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	== Inverter AND Gate ==		== Inverter AND Gate ==
	[[File:Inverter AND.jpg\|thumb\|[[AND Gate]]]]		[[File:Inverter AND.jpg\|thumb\|[[AND Gate]]\|240x240px]]
	An '''AND gate''' is a basic digital logic component whose output will be '''ON''' if '''all''' its inputs are '''ON'''.		An '''AND gate''' is a basic digital logic component whose output will be '''ON''' if '''all''' its inputs are '''ON'''.

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	The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.		The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.







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	== Inverter OR Gate ==		== Inverter OR Gate ==
	[[File:Inverter OR (Updated).jpg\|thumb\|[[OR Gate]]]]		[[File:Inverter OR (Updated).jpg\|thumb\|[[OR Gate]]\|200x200px]]
	An '''OR Gate''' is a basic digital logic component whose output will be '''ON''' if '''any''' of its inputs are '''ON'''.		An '''OR Gate''' is a basic digital logic component whose output will be '''ON''' if '''any''' of its inputs are '''ON'''.

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	The Inverter OR gate has a latency of 3 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 3 ticks later.		The Inverter OR gate has a latency of 3 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 3 ticks later.





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	== Inverter XOR Gate ==		== Inverter XOR Gate ==
	[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]]]		[[File:Inverter XOR.jpg\|thumb\|[[XOR Gate]]\|200x200px]]
	An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.		An '''XOR Gate''' is a basic digital logic component whose output will be '''ON''' if only '''one''' input is '''ON'''.

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	The Inverter XOR gate has a latency of 3 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 3 ticks later.		The Inverter XOR gate has a latency of 3 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 3 ticks later.







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	== Inverter NAND Gate ==		== Inverter NAND Gate ==
	[[File:Inverter NAND.jpg\|thumb\|[[NAND Gate]]]]		[[File:Inverter NAND.jpg\|thumb\|[[NAND Gate]]\|241x241px]]
	A '''NAND gate''' is a basic digital logic component whose output will be '''OFF''' if '''all''' its inputs are '''ON'''.		A '''NAND gate''' is a basic digital logic component whose output will be '''OFF''' if '''all''' its inputs are '''ON'''.

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	== Inverter NOR Gate ==		== Inverter NOR Gate ==
	[[File:Inverter NOR.jpg\|thumb\|[[NOR Gate]]]]		[[File:Inverter NOR.jpg\|thumb\|[[NOR Gate]]\|200x200px]]
	A '''NOR Gate''' is a basic digital logic component whose output will be '''OFF''' if '''any''' of its inputs are '''ON'''.		A '''NOR Gate''' is a basic digital logic component whose output will be '''OFF''' if '''any''' of its inputs are '''ON'''.

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	The Inverter NOR gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''inactive''' 2 ticks later.		The Inverter NOR gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''inactive''' 2 ticks later.







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	== Inverter XNOR Gate ==		== Inverter XNOR Gate ==
	[[File:Inverter XNOR.jpg\|thumb\|[[XNOR Gate]]]]		[[File:Inverter XNOR.jpg\|thumb\|[[XNOR Gate]]\|200x200px]]
	An '''XNOR Gate''' is a basic digital logic component whose output will be '''ON''' if all inputs are the same.		An '''XNOR Gate''' is a basic digital logic component whose output will be '''ON''' if all inputs are the same.

FoxFireFive at 20:08, 7 September 2025

2025-09-07T20:08:14Z

← Older revision		Revision as of 20:08, 7 September 2025
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	The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.		The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.

FoxFireFive at 20:08, 7 September 2025

2025-09-07T20:08:05Z

← Older revision		Revision as of 20:08, 7 September 2025
Line 10:		Line 10:

	The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.		The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.

FoxFireFive: Undo revision 384 by FoxFireFive (talk)

2025-09-07T20:07:58Z

Undo revision 384 by FoxFireFive (talk)

← Older revision		Revision as of 20:07, 7 September 2025
Line 10:		Line 10:

	The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.		The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.

FoxFireFive at 20:07, 7 September 2025

2025-09-07T20:07:50Z

← Older revision		Revision as of 20:07, 7 September 2025
Line 10:		Line 10:

	The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.		The Inverter AND gate has a latency of 2 ticks, so in the instance when all inputs are '''ON''', the output will become '''active''' 2 ticks later.