Random-access memory - Revision history

DjSapsan: removed stub

2025-09-27T14:57:32Z

removed stub

← Older revision		Revision as of 14:57, 27 September 2025
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	~~{{stub}}~~
	{{RAM}}		{{RAM}}

DjSapsan: RAM construction

2025-09-14T15:41:07Z

RAM construction

← Older revision		Revision as of 15:41, 14 September 2025
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	It is possible to use a single [[decoder]] to select the address, but in this example two decoders are used to specify the row and the column of the memory matrix. This makes the structure easier to understand, and also results in decoders that are half the size.		It is possible to use a single [[decoder]] to select the address, but in this example two decoders are used to specify the row and the column of the memory matrix. This makes the structure easier to understand, and also results in decoders that are half the size.

			[[File:2-decoders-ram.png\|thumb\|right\|alt=Two 2-bit decoders placed orthogonal\|Two 2-bit decoders placed orthogonal]]
	On the screenshot, you can see the two decoders placed orthogonally. Above them is the 4-bit address input.		On the screenshot, you can see the two decoders placed orthogonally. Above them is the 4-bit address input.
	~~[[File~~:~~2-decoders-ram.png\|thumb\|~~right~~\|alt=Two 2-bit decoders placed orthogonal\|Two 2-bit decoders placed orthogonal]]~~		<div style="clear:right;"></div>

			[[File:Ram-register.png\|thumb\|right\|alt=A register for a cell\|A register for a cell]]
	For each cell, we use a simple 8-bit [[register]], shown in the next screenshot.		For each cell, we use a simple 8-bit [[register]], shown in the next screenshot.
	It has one [[AND]] gate to combine the row and column signals. This enables the register if it is at the selected intersection.		It has one [[AND_Gate\|AND]] gate to combine the row and column signals. This enables the register if it is at the selected intersection.
	It also has a separate signal for writing data and another for reading.		It also has a separate signal for writing data and another for reading.
	~~[[File~~:~~Ram-register.png\|thumb\|~~right~~\|alt=A register for a cell\|A register for a cell]]~~		<div style="clear:right;"></div>

			[[File:Ram-stage-2.png\|thumb\|right\|alt=16 cells placed in a grid\|16 cells placed in a grid]]
	This register is copied 16 times and arranged into a 4×4 grid. The result is shown on the next screenshot.		This register is copied 16 times and arranged into a 4×4 grid. The result is shown on the next screenshot.
	~~[[File~~:~~Ram-stage-2.png\|thumb\|~~right~~\|alt=16 cells placed in a grid\|16 cells placed in a grid]]~~		<div style="clear:right;"></div>

			[[File:Ram-stage-3.png\|thumb\|right\|alt=Address and signal wires connected\|Address and signal wires connected]]
	The next step is connecting wires from the decoders to the cells, row by row and column by column.		The next step is connecting wires from the decoders to the cells, row by row and column by column.
	Wires are routed in 3D on top of the cells.		Wires are routed in 3D on top of the cells.
	Write and Read signals are also added. The new wiring is highlighted in yellow. The top-left cell (address 0) is selected, but it will not perform any operation unless a Write or Read signal is activated.		Write and Read signals are also added. The new wiring is highlighted in yellow. The top-left cell (address 0) is selected, but it will not perform any operation unless a Write or Read signal is activated.
	~~[[File~~:~~Ram-stage-3~~.~~png\|thumb\|right\|alt=Address~~ and ~~signal wires~~ connected~~\|Address~~ and ~~signal wires connected]]~~		<div style="clear:right;"></div>

			The last step is connecting the data inputs and outputs.
			The input is placed on the top, and all bits are connected to the corresponding inputs of every cell.
			The same is done for the output, which is placed on the bottom.

			Note that the input and output bits are shared. This is not a problem as long as reading and writing are not performed at the same time.

			The final screenshot shows the completed RAM circuit. It has 2 cells with stored data, and it is currently reading from the cell at address 6.

	~~The last step is connecting the data input and output~~.		[[File:Ram-final.png\|frame\|center\|alt=Completed RAM circuit, reading data\|Completed RAM circuit, reading data]]
	~~The input will be placed on the top~~, ~~and all input bits must be connected to the corresponding inputs of every cell.~~
	~~The same is done for the output~~, ~~except it will be placed on the bottom.~~

	== See also ==		== See also ==
	* [[Mods:CheeseUtilMod\|CheeseUtilMod]] - a mod with RAM components		* [[Mods:CheeseUtilMod\|CheeseUtilMod]] - a mod with RAM components

DjSapsan: /* Construction */

2025-09-14T15:15:28Z

Construction

@@ Line 30: / Line 30: @@
 == Construction ==
 == See also ==
 * [[Mods:CheeseUtilMod|CheeseUtilMod]] - a mod with RAM components

DjSapsan: changes

2025-09-12T23:25:21Z

changes

← Older revision		Revision as of 23:25, 12 September 2025
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	{{RAM}}		{{RAM}}

	RAM is composed of multiple cells that store data ~~and~~ accessed by address.<br>		'''RAM''' is composed of multiple cells that store data, accessed by an address.<br>
	It has 4 inputs:		It has 4 inputs:
	#Data input		# Data input
	#Address input		# Address input
	#Write signal		# Write signal
	#Read signal		# Read signal
	And 1 output:		And 1 output:
	#Data output		# Data output

	~~Building a~~ RAM ~~from scratch~~ is ~~the best way to start learning logic and computers, as well as get familiar with building circuits in ''Logic World''~~.		Each cell in RAM is essentially a [[register]].

	~~RAMs can have drastically different designs~~, ~~have different specifications and [[Optimization\|optimized]] for speed/size or even beauty~~. ~~RAM designs are specified by the following parameters:~~		Building a RAM from scratch is one of the best ways to start learning logic and computers, as well as to get familiar with circuit construction in ''Logic World''.
	~~#Address size~~
	~~#Data size~~
	~~#Delay during retrieving/storing data~~
	~~#Speed between sequential operations~~

	~~'''Address~~ and ~~data'''~~ size ~~is determined by number of bits. The total number of combinations~~, or~~, in other words,~~ the ~~largest number it can handle with '''n''' bits is <math>2^n<~~/~~math> .~~		RAMs can have very different designs, specifications, and can be [[Optimization\|optimized]] for speed, size, or even aesthetics. RAM designs are usually specified by the following parameters:
			# Address size
			# Data size
			# Delay during retrieving/storing data
			# Speed between sequential operations

	'''~~Delay~~''' ~~during retrieving/storing data~~ is ~~a delay between~~ the ~~read/write signal is turned {{on}} and when the data~~ is ~~retrieved~~/~~stored for a singular operation~~.		'''Address and data size''' is determined by the number of bits. The total number of combinations using '''n''' bits is <math>2^n</math>.

	'''~~Speed~~''' between ~~sequential operations~~ is ~~how fast it can run multiple sequential operations. The speed~~ is ~~<math>\ge</math> delay~~.		'''Delay''' during retrieving/storing data is the time between when the read/write signal is turned {{on}} and when the data is retrieved or stored for a single operation.

	This article will ~~show~~ a ~~simplest~~ RAM with 4 bits for address and 8 bits for data.		'''Speed between sequential operations''' is how fast the RAM can run multiple sequential operations. The delay between multiple operations is always <math>\ge</math> the delay for a single operation.

			This article will demonstrate a simple RAM with 4 bits for address and 8 bits for data.

	== Construction ==		== Construction ==

DjSapsan: RAM stub

2025-09-12T23:14:17Z

RAM stub

New page

{{stub}}
{{RAM}}

RAM is composed of multiple cells that store data and accessed by address.<br>
It has 4 inputs:
#Data input
#Address input
#Write signal
#Read signal
And 1 output:
#Data output

Building a RAM from scratch is the best way to start learning logic and computers, as well as get familiar with building circuits in ''Logic World''.

RAMs can have drastically different designs, have different specifications and [[Optimization|optimized]] for speed/size or even beauty. RAM designs are specified by the following parameters:
#Address size
#Data size
#Delay during retrieving/storing data
#Speed between sequential operations

'''Address and data''' size is determined by number of bits. The total number of combinations, or, in other words, the largest number it can handle with '''n''' bits is <math>2^n</math> .

'''Delay''' during retrieving/storing data is a delay between the read/write signal is turned {{on}} and when the data is retrieved/stored for a singular operation.

'''Speed''' between sequential operations is how fast it can run multiple sequential operations. The speed is <math>\ge</math> delay.

This article will show a simplest RAM with 4 bits for address and 8 bits for data.

== Construction ==

== See also ==
* [[Mods:CheeseUtilMod|CheeseUtilMod]] - a mod with RAM components