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		<title>DjSapsan: Created article about registers</title>
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		<summary type="html">&lt;p&gt;Created article about registers&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;{{Register}}&lt;br /&gt;
  &lt;br /&gt;
It is one of the most basic memory circuits in &amp;#039;&amp;#039;Logic World&amp;#039;&amp;#039; and serves as a building block for [[Random-access_memory|RAM]], [[CPU]]s, and many other digital systems.  &lt;br /&gt;
Sometimes registers are called cells.&lt;br /&gt;
&lt;br /&gt;
== Overview ==&lt;br /&gt;
&lt;br /&gt;
A register can store data and output it later on demand.  &lt;br /&gt;
Each register has the following connections:&lt;br /&gt;
# Data input&lt;br /&gt;
# Write signal&lt;br /&gt;
# Read signal  &lt;br /&gt;
And the output:&lt;br /&gt;
# Data output&lt;br /&gt;
&lt;br /&gt;
[[File:Register-basic.png|thumb|right|alt=Basic 8-bit register|Basic 8-bit register using D Latches]]&lt;br /&gt;
Registers are often used to hold intermediate results, counters, addresses, or any temporary data in larger circuits.  &lt;br /&gt;
In some cases, the data inside the register is treated as multiple values.  &lt;br /&gt;
&amp;lt;div style=&amp;quot;clear:right;&amp;quot;&amp;gt;&amp;lt;/div&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Variants ==&lt;br /&gt;
Simple registers read or write all bits simultaneously.  &lt;br /&gt;
However, there are different variations that differ by design or purpose. Common variants include:&lt;br /&gt;
&lt;br /&gt;
* &amp;#039;&amp;#039;&amp;#039;Shift register&amp;#039;&amp;#039;&amp;#039; — supports shifting bits inside on command. Variations include shifting to the left, right, or both. Shifting can be rotational or non-rotational.&lt;br /&gt;
* &amp;#039;&amp;#039;&amp;#039;Parallel-in serial-out (PISO)&amp;#039;&amp;#039;&amp;#039; — bits are stored all at once, but read serially, bit by bit.&lt;br /&gt;
* &amp;#039;&amp;#039;&amp;#039;Serial-in parallel-out (SIPO)&amp;#039;&amp;#039;&amp;#039; — bits are stored one by one, but read all at once.&lt;br /&gt;
* &amp;#039;&amp;#039;&amp;#039;Serial-in serial-out (SISO)&amp;#039;&amp;#039;&amp;#039; — bits are stored one by one and read serially, bit by bit.&lt;br /&gt;
&lt;br /&gt;
== Construction ==&lt;br /&gt;
Registers are built using trigger or latch components. There are many variants, and any of them can be used to construct a register.  &lt;br /&gt;
The simplest option is the [[D_Latch|D Latch]]. A register that stores multiple bits using D Latches is constructed by placing a row of D Latches and connecting all storage and read circuits together. The example is shown in the first screenshot above.  &lt;br /&gt;
Serial variations are constructed by connecting D Latches to each other in series instead of in parallel.&lt;br /&gt;
&lt;br /&gt;
=== Write operation ===&lt;br /&gt;
When the write input is active, the register copies its data input into its internal storage. The value remains stored even if the write signal is turned {{off}}.&lt;br /&gt;
&lt;br /&gt;
=== Read operation ===&lt;br /&gt;
[[File:register-RW.png|thumb|right|alt=8-bit register|An 8-bit register with read/write controls]]&lt;br /&gt;
All memory elements have the stored bit always active, so for better control over reading, especially when many registers share the same data bus, you may need to add an additional part to actually send the stored data. This is done by attaching outputs to [[AND_Gate|AND gates]] or [[relay|relays]].  &lt;br /&gt;
In serial-out variations, only the last one element is the output.  &lt;br /&gt;
&amp;lt;div style=&amp;quot;clear:right;&amp;quot;&amp;gt;&amp;lt;/div&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Example usage ==&lt;br /&gt;
&lt;br /&gt;
Registers are essential in circuits that need to remember or reuse values:&lt;br /&gt;
* Holding the current instruction in a [[CPU]]&lt;br /&gt;
* Holding bit flags&lt;br /&gt;
* Sending or receiving data over distance&lt;br /&gt;
* Storing a loop counter  &lt;br /&gt;
* Acting as temporary memory, like a [[cache]] for [[RAM]]    &lt;br /&gt;
&lt;br /&gt;
== See also ==&lt;br /&gt;
* [[Random-access_memory|RAM]]&lt;br /&gt;
* [[Trigger]]&lt;br /&gt;
* [[Flip Flop]]&lt;br /&gt;
* [[Latch]]&lt;/div&gt;</summary>
		<author><name>DjSapsan</name></author>
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