Tick - Revision history

N00basaurus: Updated the summary to go into detail about wires transmitting signals in the same tick

2025-10-06T05:00:56Z

Updated the summary to go into detail about wires transmitting signals in the same tick

← Older revision		Revision as of 05:00, 6 October 2025
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	Most [[component\|components]] take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs.		Most [[component\|components]] take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs.
	~~{{Todo\|Add more general information about timing}}~~[[File:And gate activation delay.png\|thumb\|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]
			It's important to note that only components introduce a tick delay. Signals traveling through [[Wiring]] are instant, no matter how long the wire is.

			This is also true even if the wire sends its signal through a [[Peg]] or a [[Socket]].

			If the state of a components output is updated, the connected inputs of other components will be updated in the same tick.
			[[File:And gate activation delay.png\|thumb\|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]

	[[File:XOR gate activation delay.png\|thumb\|A demonstration of two XOR gates being activated. The top XOR gate has one of its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom XOR gate has had one of its inputs active for at least 1 tick, and its output is therefore active.]]		[[File:XOR gate activation delay.png\|thumb\|A demonstration of two XOR gates being activated. The top XOR gate has one of its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom XOR gate has had one of its inputs active for at least 1 tick, and its output is therefore active.]]

Felipe: use keys template

2025-09-10T20:51:22Z

use keys template

← Older revision		Revision as of 20:51, 10 September 2025
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	While every components state is calculated and updated at each tick, the number of ticks that occur in a second can be adjusted from as low as 1 tick per second (tps) all the way up to 10,000 tps.		While every components state is calculated and updated at each tick, the number of ticks that occur in a second can be adjusted from as low as 1 tick per second (tps) all the way up to 10,000 tps.

	Adjustments can be made by opening up the simulation controls menu. By default, this is the ~~<code>f9</code>~~ button.		Adjustments can be made by opening up the simulation controls menu. By default, this is the {{keys\|F9}} button.


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	You can also pause/resume the simulation or step the simulation using hotkeys on your keyboard.		You can also pause/resume the simulation or step the simulation using hotkeys on your keyboard.

	By default, this is ~~<code>f10</code>~~ to pause/resume the simulation, and ~~<code>~~shift+~~f10</code>~~ to step the simulation when paused.		By default, this is {{keys\|F10}} to pause/resume the simulation, and {{keys\|shift+F10}} to step the simulation when paused.
	{{Todo\|Add screenshots of the simulation controls menu}}		{{Todo\|Add screenshots of the simulation controls menu}}

N00basaurus: Added a paragraph on controlling the simulation speed

2025-09-10T20:16:55Z

Added a paragraph on controlling the simulation speed

← Older revision		Revision as of 20:16, 10 September 2025
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	Most [[component\|components]] take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs.		Most [[component\|components]] take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs.
			{{Todo\|Add more general information about timing}}[[File:And gate activation delay.png\|thumb\|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]

	[[File:~~And~~ gate activation delay.png\|thumb\|A demonstration of two ~~AND~~ gates being activated. The top ~~AND~~ gate has ~~both~~ its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom ~~AND~~ gate has had ~~both~~ its inputs active for at least 1 tick, and its output is therefore active.]]		[[File:XOR gate activation delay.png\|thumb\|A demonstration of two XOR gates being activated. The top XOR gate has one of its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom XOR gate has had one of its inputs active for at least 1 tick, and its output is therefore active.]]

			== Simulation Speed ==
			While every components state is calculated and updated at each tick, the number of ticks that occur in a second can be adjusted from as low as 1 tick per second (tps) all the way up to 10,000 tps.

			Adjustments can be made by opening up the simulation controls menu. By default, this is the <code>f9</code> button.

	~~[[File:XOR gate activation delay.png\|thumb\|A demonstration of two XOR gates being activated. The top XOR gate has one of its inputs active~~, ~~but its output is not yet active because a delay of~~ 1 tick ~~has not yet passed~~. ~~The bottom XOR gate has had one of its inputs active~~ for ~~at least 1 tick~~, and ~~its output is therefore active~~.]]
			Additionally, the simulation can be paused entirely, and stepped 1 tick at a time from the control menu. Useful for debugging circuits that don't behave like you'd expect.

			You can also pause/resume the simulation or step the simulation using hotkeys on your keyboard.

			By default, this is <code>f10</code> to pause/resume the simulation, and <code>shift+f10</code> to step the simulation when paused.
			{{Todo\|Add screenshots of the simulation controls menu}}

Jimmy at 22:42, 8 September 2025

2025-09-08T22:42:23Z

← Older revision		Revision as of 22:42, 8 September 2025
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	[[File:And gate activation delay.png\|thumb\|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]		[[File:And gate activation delay.png\|thumb\|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]

			[[File:XOR gate activation delay.png\|thumb\|A demonstration of two XOR gates being activated. The top XOR gate has one of its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom XOR gate has had one of its inputs active for at least 1 tick, and its output is therefore active.]]

Jimmy: Created page with "{{stub}} A '''tick''' refers to one step of the game's logic simulation. Most components take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs. File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active becaus..."

2025-09-08T22:11:50Z

Created page with "{{stub}} A '''tick''' refers to one step of the game's logic simulation. Most components take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs. File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active becaus..."

New page

{{stub}}

A '''tick''' refers to one step of the game's logic simulation.

Most [[component|components]] take one tick to update the state of their output after their input changes state. Thus, on some ticks, the state of a component's outputs will be "wrong" compared to the state of its inputs.

[[File:And gate activation delay.png|thumb|A demonstration of two AND gates being activated. The top AND gate has both its inputs active, but its output is not yet active because a delay of 1 tick has not yet passed. The bottom AND gate has had both its inputs active for at least 1 tick, and its output is therefore active.]]