Random-access memory

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Random-access memory

In Logic World, Random-access memory (RAM) is a circuit that can store and load data on demand.

Unlike ROM, the contents of RAM can be changed at any time by writing new data to it.

Unlike non-random-access memory, access can be performed in any order with a constant delay for each cell.

RAM is composed of multiple cells that store data and accessed by address.
It has 4 inputs:

1. Data input
2. Address input
3. Write signal
4. Read signal

And 1 output:

1. Data output

Building a RAM from scratch is the best way to start learning logic and computers, as well as get familiar with building circuits in Logic World.

RAMs can have drastically different designs, have different specifications and optimized for speed/size or even beauty. RAM designs are specified by the following parameters:

1. Address size
2. Data size
3. Delay during retrieving/storing data
4. Speed between sequential operations

Address and data size is determined by number of bits. The total number of combinations, or, in other words, the largest number it can handle with n bits is $2^n$ .

Delay during retrieving/storing data is a delay between the read/write signal is turned ON and when the data is retrieved/stored for a singular operation.

Speed between sequential operations is how fast it can run multiple sequential operations. The speed is $\ge$ delay.

This article will show a simplest RAM with 4 bits for address and 8 bits for data.

See also

• CheeseUtilMod - a mod with RAM components