Random-access memory: Difference between revisions

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Random-access memory: In Logic World, Random-access memory (RAM) is a circuit that can store and load data on demand.; Unlike ROM, the contents of RAM can be changed at any time by writing new data to it.; Unlike non-random-access memory, access can be performed in any order with a constant delay for each cell.

RAM is composed of multiple cells that store data, accessed by an address.
It has 4 inputs:

Data input
Address input
Write signal
Read signal

And 1 output:

Data output

Each cell in RAM is essentially a register.

Building a RAM from scratch is one of the best ways to start learning logic and computers, as well as to get familiar with circuit construction in Logic World.

RAMs can have very different designs, specifications, and can be optimized for speed, size, or even aesthetics. RAM designs are usually specified by the following parameters:

Address size
Data size
Delay during retrieving/storing data
Speed between sequential operations

Address and data size is determined by the number of bits. The total number of combinations using n bits is $2^{n}$ .

Delay during retrieving/storing data is the time between when the read/write signal is turned ON and when the data is retrieved or stored for a single operation.

Speed between sequential operations is how fast the RAM can run multiple sequential operations. The delay between multiple operations is always $\geq$ the delay for a single operation.

This article will demonstrate a simple RAM with 4 bits for address and 8 bits for data.

@@ Line 2: / Line 2: @@
 {{RAM}}
-RAM is composed of multiple cells that store data and accessed by address.<br>
+'''RAM''' is composed of multiple cells that store data, accessed by an address.<br>
 It has 4 inputs:
-#Data input
+# Data input
-#Address input
+# Address input
-#Write signal
+# Write signal
-#Read signal
+# Read signal
 And 1 output:
-#Data output
+# Data output
-Building a RAM from scratch is the best way to start learning logic and computers, as well as get familiar with building circuits in ''Logic World''.
+Each cell in RAM is essentially a [[register]].
-RAMs can have drastically different designs, have different specifications and [[Optimization|optimized]] for speed/size or even beauty. RAM designs are specified by the following parameters:
+Building a RAM from scratch is one of the best ways to start learning logic and computers, as well as to get familiar with circuit construction in ''Logic World''.
-#Address size
-#Data size
-#Delay during retrieving/storing data
-#Speed between sequential operations
-'''Address and data''' size is determined by number of bits. The total number of combinations, or, in other words, the largest number it can handle with '''n''' bits is <math>2^n</math> .
+RAMs can have very different designs, specifications, and can be [[Optimization|optimized]] for speed, size, or even aesthetics. RAM designs are usually specified by the following parameters:
+# Address size
+# Data size
+# Delay during retrieving/storing data
+# Speed between sequential operations
-'''Delay''' during retrieving/storing data is a delay between the read/write signal is turned {{on}} and when the data is retrieved/stored for a singular operation.
+'''Address and data size''' is determined by the number of bits. The total number of combinations using '''n''' bits is <math>2^n</math>.
-'''Speed''' between sequential operations is how fast it can run multiple sequential operations. The speed is <math>\ge</math> delay.
+'''Delay''' during retrieving/storing data is the time between when the read/write signal is turned {{on}} and when the data is retrieved or stored for a single operation.
-This article will show a simplest RAM with 4 bits for address and 8 bits for data.
+'''Speed between sequential operations''' is how fast the RAM can run multiple sequential operations. The delay between multiple operations is always <math>\ge</math> the delay for a single operation.
+This article will demonstrate a simple RAM with 4 bits for address and 8 bits for data.
 == Construction ==

Revision as of 23:25, 12 September 2025

Construction

See also