Random-access memory

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Random-access memory

In Logic World, Random-access memory (RAM) is a circuit that can store and load data on demand.

Unlike ROM, the contents of RAM can be changed at any time by writing new data to it.

Unlike non-random-access memory, access can be performed in any order with a constant delay for each cell.

RAM is composed of multiple cells that store data, accessed by an address.
It has 4 inputs:

1. Data input
2. Address input
3. Write signal
4. Read signal

And 1 output:

1. Data output

Each cell in RAM is essentially a register.

Building a RAM from scratch is one of the best ways to start learning logic and computers, as well as to get familiar with circuit construction in Logic World.

RAMs can have very different designs, specifications, and can be optimized for speed, size, or even aesthetics. RAM designs are usually specified by the following parameters:

1. Address size
2. Data size
3. Delay during retrieving/storing data
4. Speed between sequential operations

Address and data size is determined by the number of bits. The total number of combinations using n bits is $2^n$.

Delay during retrieving/storing data is the time between when the read/write signal is turned ON and when the data is retrieved or stored for a single operation.

Speed between sequential operations is how fast the RAM can run multiple sequential operations. The delay between multiple operations is always $\ge$ the delay for a single operation.

This article will demonstrate a simple RAM with 4 bits for address and 8 bits for data.

See also

• CheeseUtilMod - a mod with RAM components