Finite State Machine
A Finite State Machine is a circuit that will produce a sequence of states and output signals depending on input conditions and a state graph.
It's constructed using either a ROM, or a Programmable Logic Array, by taking some or all of the components outputs and connecting them to some or all of its inputs through a Register.
The component can then be used to create mappings of one list of states to another.
For example, you could map the states 1 to 2, 2 to 3, 3 to 5, 5 to 8, and 8 to 13, and as you pulse the register, you will see the sequence 1, 2, 3, 5, 8, 13 appear.
Where state machines become really powerful though is when you map 13 to 1 , doing so creates a loop in the graph, and allows the sequence to repeat indefinitely.
You can have extra inputs to act as flags to check, allowing you to create conditional branches.
For example, you could map 3 to 5 if the input fib was on, and you could map 3 to 4 if the fib input was off.
In cases where an input is not checked, but is actually ignored, you'll need to implement the same state mapping twice, once for if the condition is on, and again for if the condition is off, in order for the transition from state to state to happen regardless of the conditions state.
This is only true if you're using a ROM to represent your state graph. If you are using a Programmable Logic Array, you can just not connect the input.
A state machine can also produce extra outputs in each state.
This can be done by connecting a Lookup Table to the output of the state register, and mapping each valid state to a combination of outputs. This setup is referred to as a Moore machine.
Alternatively, you can give the state machine more outputs and synchronize them with another register. This allows the state machine to pick the next combination of outputs at the transition. This setup is referred to as a Mealy machine.